Method of making local interconnections for dynamic random acces

Details Method of making local interconnections for dynamic random acces Method of making local interconnections for dynamic random acces

1999-02-12

1999-12-14

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438592, 438655, 438663, H01L 2128, H01L 21336

Patent

active

060017171

ABSTRACT:
A method for making low-resistance contacts between polycide layers for local interconnections is achieved. The method is particularly useful for making low contact resistance R.sub.c between the tungsten polycide layers for local interconnections on the periphery of the DRAM chip. A first polycide layer is patterned to form FET gate electrodes and portions of local interconnections. An interlevel dielectric layer is deposited over the patterned first polycide layer. Contact openings are etched in the dielectric layer to the surface of the substrate and to the first polycide layer. A second polycide layer is deposited and patterned to form bit lines in the memory cell areas of the DRAM, while concurrently forming local interconnections in the peripheral device areas. A high-temperature rapid thermal anneal (RTA) is carried out to substantially reduce the contact resistance in the contact openings over the first polycide layer in the peripheral areas. This RTA eliminates the need for overetching the first silicide in the contact holes, as commonly practiced in the prior art. The RTA of this invention with a traditional N.sub.2 anneal prior to the second polycide deposition results in a synergistic effect that further reduces the contact resistance R.sub.c.

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