Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-05-24
2003-02-25
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S112000, C438S124000, C257S678000
Reexamination Certificate
active
06524886
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to a lead frame package, and more specifically to a method of making a leadless semiconductor package.
2. Description of the Related Art
Lead frame packages have been used for a long period of time in the IC packaging industry mainly because of their low manufacturing cost and high reliability. However, as integrated circuits products move its endless pace toward both a faster speed and a smaller size, the traditional lead frame packages have become gradually obsolete for some high performance-required packages. Thus BGA (Ball Grid Array Packages) and CSP (Chip Scale Package) have emerged and become increasingly popular as a new packaging choice. The former has been widely used in IC chips that have higher I/Os and need better electrical and thermal performance than the conventional packages such as CPU and graphic chips. The latter has been widely used in mobile products of which the footprint, package profile and package weight are major concerns.
However, the lead frame package still remains its market share as a cost-effective solution for low I/O ICs. Traditional lead frame package has its limit of providing a solution for chip scale and low profile package due to the long inner leads and outer leads. Therefore, the semiconductor packaging industry develops a leadless package without outer leads such that both the foot print and the package profile can be greatly reduced.
FIG. 1
shows a bottom view of a leadless package
100
wherein the leads
110
a
are disposed at the bottom of the package as compared to the conventional gull-wing or J-leaded type package. The die pad
110
b
of the leadless package
100
is exposed from the bottom of the package thereby providing better power dissipation. Typically, there are four tie bars
110
c
being connected to the die pad
110
b.
Due to the elimination of the outer leads, the leadless package
100
is featured by lower profile and light weight. Furthermore, due to the lead length reduction, the corresponding reduction in the resistance, conductance and capacitance make the leadless package
100
very suitable for RF (radio-frequency) product packages operating in several GHz to tens of GHz frequency range. It's also a cost-effective package due to its use of existing BOM (bill of materials). All the above-mentioned properties make the current leadless packages very suitable for telecommunication products such as cellular phones, portable products such as PDA (personal digital assistant), digital cameras, and IA (Information Appliance).
The typical method for producing a leadless semiconductor chip package comprises the steps of: (A) attaching a semiconductor chip
120
onto the die pad
110
b
of a lead frame, wherein the lead frame comprises a plurality of leads
110
a
arranged about the periphery of the die pad
110
b
; (B) wire-bonding the leads of the lead frame to bonding pads on the semiconductor chip; and (C) forming a package body
130
over the semiconductor chip and the lead frame in a manner that each lead of the lead frame has at least a portion exposed from the bottom of the package body.
Typically, the package body
130
is formed from molding compound with a coefficient of thermal expansion (CTE) of 8 ppm/° C.(Alpha
1
)-32 ppm/° C.(Alpha
2
). However, the lead frame (i.e., the leads) is usually made of copper with a coefficient of thermal expansion (CTE) of 18 ppm/° C. and has a thickness of about 5 mils. The package body
130
and the leads
110
a
have a significant difference in CTE and the leads
110
a
are rather thick. Thus the package body
130
and the leads
110
a
expand and contract in different amounts along with temperature fluctuations during the curing process of the package body
130
, which often causes the leadless package
100
to fail the environment stress test.
To reduce the problems described above, the thickness of the lead frame may be reduced down to about 1 mil. However, during the whole packaging process, if the lead frame is reduced too much in thickness, it will be unable to provide sufficient strength for supporting the semiconductor chip.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of making a leadless semiconductor package which overcomes or at least reduces the problems and disadvantages associated with the above-described technique.
The method of making a leadless semiconductor package in accordance with the present invention comprising: (a) providing a lead frame including a die pad and a plurality of leads; (b) attaching a semiconductor chip to the die pad of the lead frame and electrically coupling the semiconductor chip to the leads of the lead frame; (c) forming a package body over the semiconductor chip and the lead frame in a manner that each lead of the lead frame has at least a portion exposed from the bottom of the package body; and (d) grinding the bottom of the package body as well as the exposed portions of the lead frame. Preferably, a tape is attached onto the bottom of the lead frame before proceeding to the step (b) for avoiding the mold flash problem in the molding process, and the tape is removed after completing the step (c).
It is noted that the grinding step proceeds till each lead of the lead frame is less than about 1 mil thick thereby reducing the problems due to CTE mismatch between the leads and the package body.
REFERENCES:
patent: 5172214 (1992-12-01), Castro
patent: 5286999 (1994-02-01), Chiu
patent: 5894108 (1999-04-01), Mostafazadeh et al.
patent: 6372539 (2002-04-01), Bayan et al.
patent: 6542255 (2002-09-01), Bayan et al.
Advanced Semiconductor Engineering Inc.
Coleman William David
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