Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2006-02-21
2006-02-21
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S502000
Reexamination Certificate
active
07001778
ABSTRACT:
In the manufacture of an integrated circuit, a first electrode (48) is formed on a substrate (28). In a first embodiment, a strontium bismuth tantalate layer (50) and a second electrode (52) are formed on top of the first electrode (48). Prior to the final crystallization anneal, the first electrode (48), the strontium bismuth tantalate layer (50) and the second electrode (52) are patterned. The final crystallization anneal is then performed on the substrate (28). In a second embodiment, a second layer (132) of strontium bismuth tantalate is deposited on top of the strontium bismuth tantalate layer (50) prior to the forming of the second electrode (52) on top of the first and second layers (50), (132). In a third embodiment, a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50). In a fourth embodiment, an additional rapid thermal annealing process is performed on a substrate subsequent to the patterning process and prior to the final crystallization annealing process.
REFERENCES:
patent: 5046043 (1991-09-01), Miller et al.
patent: 5418389 (1995-05-01), Watanabe
patent: 5853500 (1998-12-01), Joshi et al.
patent: 5942376 (1999-08-01), Uchida et al.
patent: 6022669 (2000-02-01), Uchida et al.
patent: 6133050 (2000-10-01), Azuma et al.
patent: 10019822 (2001-10-01), None
Ogata, N. et al: “Fine-Graned SRBI2TA209 Thin Films By Low Temperature Annealing”, Extended Abstracts of The International Conference On Solid State Devices And Materials, Japan Society Of Applied Physics. Tokyo, Japan, Sep. 1, 1997, pp. 40-41, XP000728016.
Horikawa, T. et al: Effects Of Post-Annealing On Dielectric Properties Of (BA, SR) TI03 Thin Films Prepared By Liquid Source Chemical Vapor Deposition, IEICE Transactions On Electronics, Institutes Of Electronics Information And Comm. Eng., Tokyo, Japan, vol. E81-C, No. 4, Apr. 1998, pp. 497-503, XP00083374, ISSN: 0916-8524.
Shimakawa, Y. et al: “Crystal Structures And Ferroelectric Properties Of SRBI2TA209 And SRO.BB12.2TA209”, Applied Physics Letters, American Institute Of Physics New Yor, US. Vol. 74, NO. 13, Mar. 29, 1999, pp. 1904-1906, xp000827171, ISSN: 0003-6951.
Joshi Vikram
Karasawa Junichi
Chaudhari Chandra
Patton & Boggs LLP
Seiko Epson Corporation
Symetrix Corporation
LandOfFree
Method of making layered superlattice material with improved... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making layered superlattice material with improved..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making layered superlattice material with improved... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3686462