Method of making interconnections between a multi-layer chip sta

Details Method of making interconnections between a multi-layer chip sta Method of making interconnections between a multi-layer chip sta

1998-07-13

2000-08-22

Chaudhuri, Olik

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

438124, 438126, 438127, H01L 2148

Patent

active

061071218

ABSTRACT:
A semiconductor device package and method includes a thick, integrated circuit chip stack having a substantially planar bottom surface with a plurality of terminals. A carrier substrate is provided, also having a substantially planar surface, and being adapted to mount the chip stack. The substrate has a plurality of terminals and may preferably be made of a metallized ceramic. The terminals of the chip stack are adapted to be connected to the terminals of the substrate. Means are provided for mounting the chip stack on the substrate, as well as means for making electrical connections between the terminals of the chip stack and the terminals of the substrate. Finally, encapsulating means are used for supporting and maintaining the chip stack mounted on the carrier substrate. J leads connect the substrate to a circuit card.

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