Semiconductor device manufacturing: process – Masking – Subphotolithographic processing
Reexamination Certificate
2000-01-26
2002-03-26
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Masking
Subphotolithographic processing
C438S183000, C438S185000, C438S197000, C438S301000, C438S303000, C438S305000, C438S306000, C438S587000, C438S595000, C438S597000
Reexamination Certificate
active
06362117
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to fabrication of an integrated circuit and, more particularly, to fabrication of an integrated circuit having components which are very closely spaced.
BACKGROUND OF THE INVENTION
When fabricating an integrated circuit, it is often desirable to have certain components of the integrated circuit spaced from each other by distances which are relatively small. For example, there are situations where several parallel lines include two groups of lines which are interleaved and which respectively carry two power supply voltages, or respectively carry a power supply voltage and a system ground. In situations of this type, it can be advantageous to have a very close spacing between the lines, for example to obtain a high capacitive coupling effect which filters out noise. As another example, where several transistors are coupled in series, it can be advantageous to have the gate structures for the transistors arranged with very close spacing, in order to reduce series resistance, and in order to reduce the capacitance at nodes between the transistors. Yet another consideration, which comes up in many applications, is that reduction of the spacing between components would result in reduction of the overall size or area of the integrated circuit, which can be advantageous.
As a practical manner, however, there are limitations on the capability to fabricate component parts of an integrated circuit which are very closely spaced. For example, there are mechanical considerations which limit the ability to achieve close alignment tolerances between successive lithographic steps that are involved in the fabrication of an integrated circuit. Moreover, where close lithographic alignment tolerances are used in an attempt to achieve close spacing, it can necessitate a level of precision which increases the overall cost of the fabrication process.
In addition, there are situations in which the degree of spacing that can be achieved using existing lithographic techniques is less than what would be desirable. For example, there are situations in which it would be desirable to have component parts of an integrated circuit spaced by distances which are sublithographic, or in other words distances which involve considerations that exceed existing lithographic capabilities.
Thus, while there are existing techniques for fabricating integrated circuits so that certain component parts are somewhat closely spaced, at least in terms of existing lithographic capabilities, and while these known techniques have been generally adequate for their intended purposes, they have not been satisfactory in all respects. In this regard, there are situations in which it would be desirable to fabricate component parts that are relatively closely spaced, but through the use of techniques which do not necessitate the level of precision and cost associated with existing techniques that approach the limits of lithographic capabilities. Further, it would be desirable for certain applications to be able to fabricate component parts within an integrated circuit which are spaced by a distance smaller than can be achieved by known techniques, including sublithographic distances.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for an integrated circuit, and a method of making it, where components of the integrated circuit are very closely spaced, and in some cases by distances which are sublithographic.
According to a first form of the present invention, this need is met by a method of making an integrated circuit, and by an integrated circuit made according to the method, where the method includes: providing a structure having a top surface; forming spaced first and second sections on the top surface, the first and second sections respectively having first and second side surfaces thereon which face each other; forming a first sidewall on the first side surface; and forming a second sidewall on the second side surface. A third section is formed between the first and second sidewalls, including the steps of introducing a selected material between the first and second sidewalls, and removing any portion of the selected material which is higher than upper ends of the first and second sidewalls.
According to a different form of the present invention, the need is met by an integrated circuit which includes: a structure having a top surface; spaced first and second sections disposed on the top surface, and a third section disposed on the top surface between the first and second sections, the first and third sections being spaced from each other by a distance which is sublithographic, and the second and third sections being spaced from each other by a distance which is sublithographic. A first sidewall is disposed between the first and third sections, and a second sidewall is disposed between the second and third sections.
REFERENCES:
patent: 5640032 (1997-06-01), Tomioka
patent: 5670427 (1997-09-01), Cho
patent: 5892707 (1999-04-01), Noblee
patent: 6037253 (2000-03-01), Chung
patent: 6271095 (2001-08-01), Yu
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