Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-07-30
2001-03-20
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S701000, C438S713000
Reexamination Certificate
active
06204186
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices, and, more particularly, to methods of making capacitors.
BACKGROUND OF THE INVENTION
Capacitors are used extensively in electronic devices for storing an electric charge. A capacitor includes two conductive plates or electrodes separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, depends upon the area of the plates, the distance between them, and the dielectric value of the insulator. Capacitors may be formed within a semiconductor device, such as, for example, a dynamic random access memory (DRAM) or an embedded DRAM.
As semiconductor memory devices become more highly integrated, the area occupied by the capacitor of a DRAM storage cell is reduced, thus decreasing the capacitance of the capacitor due to a smaller electrode surface area. However, a relatively large capacitance is desired to prevent loss of stored information. Therefore, it is desirable to reduce the cell dimensions and yet obtain a high capacitance, which achieves both high cell integration and reliable operation.
One technique for increasing the capacitance while maintaining the high integration of the storage cells is directed toward the shape of the capacitor electrodes. In this technique, the polysilicon layer of the capacitor electrodes may have protrusions, fins, cavities, etc., to increase the surface area of the capacitor electrode, thereby increasing its capacitance while maintaining the small area occupied on the substrate surface.
Instead of forming the capacitor on the substrate surface, capacitors are also formed above the substrate, i.e., they are stacked above the substrate. The surface area of the substrate can then be used for forming transistors. U.S. Pat. No. 5,903,493 to Lee discloses a capacitor formed above a tungsten plug. The surface area of the capacitor is increased by etching a trench in the dielectric layer around the tungsten plug. The tungsten plug interfaces with an interconnection line, thus allowing different layers formed above the substrate to be connected.
The trench is patterned by conventional etching or other suitable techniques. The fundamental limit on how far the trench can be etched is determined by how well the tungsten plug is secured within the dielectric layer. Typically, the depth of the trench is limited to about one half the thickness of the dielectric layer. After the trench has been etched, a capacitor is formed above the tungsten plug. Unfortunately, if the trench is etched beyond one half the thickness of the dielectric, the tungsten plug is more likely to become loose and fall out. This physical separation between the tungsten plug and the underlying metal interconnection with interconnect line can cause open circuits to be formed resulting in complete failure of the device or circuit.
A known approach to secure the metal plug uses a metal plug with an anchor portion extending into the interconnect line. This approach uses an additional wet etch, reactive ion etch (RIE) or plasma etch to form an anchor hole in the interconnect line and below the dielectric layer.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide a method for making an integrated circuit capacitor having increased capacitance without decreasing the reliability of the capacitor.
This and other advantages, features and objects in accordance with the present invention are provided by a method of making an integrated circuit capacitor including the steps of: forming an interconnection line adjacent a substrate; depositing a first dielectric layer on the interconnection line; etching a via in the first dielectric layer, the via having a tapered width which increases in a direction toward the substrate; filling the via with a conductive metal to form a metal plug; etching a trench in the first dielectric layer around an upper portion of the metal plug; and depositing a second dielectric layer adjacent the metal plug and an upper electrode on the second dielectric layer. Preferably, a lower electrode is deposited on the metal plug. The conductive metal of the metal plug may comprise tungsten, for example.
The step of etching the via may comprise the use of directional etching and the metal plug may comprise a lower portion disposed in the first dielectric layer and having a tapered width which increases in the direction toward the substrate. Also, the upper portion of the metal plug may have a tapered width which increases in the direction toward the substrate. The tapered width of the metal plug secures or anchors the metal plug in the dielectric layer. The angle of taper may preferably be greater than about 2° and more preferably greater than about 5°.
The trench may be etched to a depth of more than one half a thickness of the first dielectric layer, e.g. greater than about 250 angstroms. The interconnection line preferably comprises a bulk conductor connected to the metal plug. Also, an uppermost surface of the metal plug and an adjacent uppermost surface of the first dielectric layer are preferably planarized.
REFERENCES:
patent: 5903493 (1999-05-01), Lee
patent: 5990507 (1999-11-01), Mochizuki et al.
patent: 6051859 (2000-04-01), Hosotani et al.
Chaudhry Samir
Chetlur Sundar Srinivasan
Layadi Nace
Roy Pradip Kumar
Vaidya Hem M.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chen Kin-Chan
Lucent Technologies - Inc.
Utech Benjamin L.
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