Method of making high density dielectric isolated gate MOS trans

Details Method of making high density dielectric isolated gate MOS trans Method of making high density dielectric isolated gate MOS trans

1984-12-21

1986-09-09

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 148 15, 148187, 148DIG82, 357 91, H01L 21308, H01L 21265

Patent

active

046100784

ABSTRACT:
There is disclosed a method of manufacturing a semiconductor device comprising a step of forming an isolation film having a patterned hole on a major surface of a semiconductor substrate of a P conductivity type, the wall of the isolation film defining the patterned hole having a large step, a step of forming a polysilicon layer on the major surface of the structure, a step of forming a first interlaid SiO.sub.2 layer on the polysilicon layer, a step of patterning the SiO.sub.2 layer and polysilicon layer using reactive ion etching process, thereby forming on the region of the substrate a gate electrode and a first SiO.sub.2 film superposed thereon, the continuous side wall of the gate electrode and first SiO.sub.2 film having a large step, a step of implanting an impurity ion into the substrate using the first SiO.sub.2 film as a mask, thereby forming an impurity diffused region of an N conductivity type in the substrate, a step of forming a second interlaid SiO.sub.2 layer on the major surface of the structure, and a step of applying reactive ion etching to the second SiO.sub.2 layer, thereby forming a contact hole in the second SiO.sub.2 layer leading to the impurity diffused region, while leaving part of the second SiO.sub.2 layer on the side walls of said isolation film, gate electrode and first SiO.sub.2 film.

REFERENCES:
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4419142 (1983-12-01), Matsukawa
patent: 4435446 (1984-03-01), Marston et al.
patent: 4441941 (1984-04-01), Nozawa
patent: 4471524 (1986-09-01), Kinsbron
patent: 4488348 (1984-12-01), Jolly
patent: 4494304 (1985-01-01), Yoshioka
Matsukawa et al., "Selective Polysilicon Oxidation Technology for VLSI Isolation," IEEE Transactions on Electron Devices, vol. Ed-29, No. 4, Apr. 1982.

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