Method of making gate wiring layer over semiconductor substrate

Details Method of making gate wiring layer over semiconductor substrate Method of making gate wiring layer over semiconductor substrate

2000-09-21

2002-04-23

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S624000, C438S692000

Reexamination Certificate

active

06376347

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-272304, filed Sep. 27, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, particularly, to a method of making a gate wiring layer of a semiconductor device.
In making a gate wiring layer on a semiconductor substrate, it has been carried out to pattern a film of a gate wiring material by dry etching.
FIG. 5D
is a cross sectional view showing a semiconductor substrate having a gate wiring layer. As shown in the drawing, an insulating layer
102
of, for example, a silicon oxide film (SiO
2
) is provided on a semiconductor substrate
101
such as a silicon substrate, and a gate wiring layer
103
is formed on the surface of the insulating film
102
. The gate wiring layer
103
is electrically connected to a capacitor formed in the semiconductor substrate
101
or a metal wiring layer (not shown) on the silicon semiconductor substrate
101
. An insulating spacer
106
of, for example, a silicon nitride (Si
3
N
4
) layer is provided on the side wall of the gate wiring layer
103
, and an insulating layer
107
of, for example, a silicon oxide (SiO
2
) layer is provided to cover the gate wiring layer
103
. The gate wiring layer
103
is formed of a material such as silicon, polycrystalline silicon (polysilicon), or tungsten, or a stacked layer of these materials.
The method of making the conventional gate wiring layer will now be described with reference to
FIGS. 5A
to
5
D. In the first step, formed successively on a semiconductor substrate
101
are a gate insulating layer
102
, a conductive layer of a gate wiring layer
103
, and an antireflection layer
104
for preventing the reflected light from acting on a photoresist layer, as shown in FIG.
5
A. The antireflection layer
104
is composed of an organic compound. Then, a photoresist layer
105
is formed on the antireflection layer
104
and patterned by a lithography technique so as to have a configuration similar to that of the gate wiring layer, as shown in FIG.
5
B. Then, using the patterned photoresist layer
105
as a mask, the antireflection layer
104
and the conductive layer are etched by dry etching to provide a gate wiring layer
103
having a predetermined pattern. After removing the photoresist layer
105
and the antireflection layer
104
, an insulating layer
106
is deposited over the substrate surface as shown in FIG.
5
C. Further, the insulating layer
106
is etched back by the dry etching to provide an insulating spacer
106
at the side wall of the gate wiring layer
103
, followed by depositing an insulating layer
107
to cover the gate wiring
103
therewith, as shown in FIG.
5
D.
When the conductive layer of the gate wiring layer
103
provided over the semiconductor substrate
101
is etched by using the photoresist layer
105
used as the mask, the etching treatment must be stopped so that the gate insulating layer
102
on the semiconductor substrate
101
is unremoved. In the case of under-etching as shown in
FIG. 6A
, a trailing configuration may be caused between the gate wiring layers, or sufficient etching may not be carried out to provide an electrical short-circuiting in the gate wiring layers. Also, in the case of over-etching as shown in
FIG. 6B
, the gate insulating layer
102
may be etched by a halogen-gas such as HBr or Cl
2
, which are contained in the etching gas used for selectively etching the conductive layer of the gate wiring layers, and the semiconductor substrate
101
may also be etched. In recent years, the gate insulating layer will be made thinner and thinner in order to increase the operating speed of the MOS transistor. As a result, it will be difficult to control the etching process of the conductive layer of the gate wiring layers without removing the gate insulating layer over the entire surface of the semiconductor substrate.
Further, the gate insulating layer interposed between the semiconductor substrate and the gate wiring layers will be subjected to plasma damage by selective etching of the conductive layer and by deposition of an insulating layer using plasma CVD (Chemical Vapor Deposition).
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of making a gate wiring layer of a semiconductor device, which permits selectively stopping the etching treatment not to etch the gate insulating layer.
Another object of the present invention is to provide a method of making a gate wiring layer of a semiconductor device, which utilizes a carbon-based layer.
Still another object of the present invention is to provide a method of making a gate wiring layer of a semiconductor device, which utilizes a carbon-based layer for preventing the gate insulating layer and the semiconductor substrate from being etched.
The present invention is directed to a method of making a gate wiring layer on a semiconductor substrate and comprises the step of forming an insulating layer of, for example, SiO
2
on a semiconductor substrate, the step of forming a carbon-based layer, the step of forming a predetermined mask on the carbon-based layer, and the step of patterning the carbon-based layer. It should be noted that the carbon-based layer is subjected to dry etching using an oxygen gas, a carbon monoxide gas or a mixed gas containing an oxygen gas, a nitrogen gas, a carbon monoxide gas and an argon gas and not containing halogen such that the etching is selectively stopped before the insulating layer is etched.
The insulating layer of, for example, SiO
2
is etched by the dry etching using a gas containing halogen such as F and Cl. However, the reactive etching does not almost proceeds, by the dry etching using a gas of oxygen, nitrogen, carbon monoxide or argon, the gas not containing the halogen, or a mixed gas thereof.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming an insulating layer on a semiconductor substrate; forming a carbon-based layer on the insulating layer; forming a mask of a predetermined pattern on the carbon-based layer; etching the carbon-based layer with a gas containing oxygen by using the mask, thereby providing an opening therein; burying a conductive material within the opening of the carbon-based layer after removing the mask therefrom; and removing the carbon-based layer.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a first insulating layer on a semiconductor substrate; forming a carbon-based layer on the first insulating layer; forming a mask having a predetermined pattern on the carbon-based layer; etching the carbon-based layer with an oxygen-containing gas to form a predetermined pattern; removing the mask and forming a second insulating layer on the first insulating layer in a manner to bury the patterned carbon-based layer; removing the carbon-based layer to form an opening in the second insulating layer; and burying a conductive material in the opening.
In this case, after the insulating layer at the bottom of the opening is removed, an insulating layer corresponding to the gate insulating layer may be formed at the bottom.
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a first insulating layer on a semiconductor substrate; forming a carbon-based layer on the first insulating layer; forming a second insulating layer on the carbon-based layer; forming a mask having a predetermined pattern on the second insulating layer; selectively removing the second insulating film by using the mask to expose the carbon-based layer; selectively etching the exposed carbon-based layer with an oxygen-containing gas to provide an

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