Method of making fast, trench isolated, planar flash EEPROMS wit

Details Method of making fast, trench isolated, planar flash EEPROMS wit Method of making fast, trench isolated, planar flash EEPROMS wit

1990-06-05

1991-07-02

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 49, 437200, 148DIG147, H01L 21283

Patent

active

050285530

ABSTRACT:
A non-volatile cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines from the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.

REFERENCES:
patent: 4597060 (1986-06-01), Mitchell et al.
patent: 4642881 (1987-02-01), Matsukawa et al.
patent: 4727043 (1988-02-01), Matsumoto et al.
patent: 4763177 (1988-08-01), Paterson
E. S. Yong, Microelectronic Devices, 1988, pp. 346-351.

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