Method of making EPROM cell with reduced programming voltage

Details Method of making EPROM cell with reduced programming voltage Method of making EPROM cell with reduced programming voltage

1983-07-22

1985-05-28

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 148187, 357 91, H01L 2122, H01L 2126

Patent

active

045198497

ABSTRACT:
An improved floating gate MOS EPROM cell which is programmable at a lower potential (12 volts) than prior art devices which often require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.

REFERENCES:
patent: 4080718 (1978-03-01), Richman
patent: 4288256 (1981-09-01), Ning et al.
patent: 4317273 (1982-03-01), Guterman et al.
patent: 4342149 (1982-08-01), Jacobs et al.
patent: 4373248 (1983-02-01), McElroy
patent: 4409727 (1983-10-01), Dalton, Jr. et al.
patent: 4426764 (1984-01-01), Kosa et al.

Affiliated with

Also associated with

Rating

Method of making EPROM cell with reduced programming voltage does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making EPROM cell with reduced programming voltage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making EPROM cell with reduced programming voltage will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-867128