Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-05-14
2001-02-06
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S629000, C438S631000, C438S633000, C438S666000
Reexamination Certificate
active
06184124
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a wiring system structure for semiconductor devices, especially to a multilevel embedded wiring system structure for an IC and a method of making the wiring system.
2. Description of Related Art
With higher integration of semiconductor devices, finer wiring systems on a substrate are desired, resulting in an decreased life time of the wiring. Therefore, there has been desired in this field a wiring system embedded in an insulating layer formed on a substrate, because that system improves the reliability of produced semiconductor chips. Further, because of a flat surface of the resulting wiring system, it is advantageous to make a multilevel wiring system by building up more than one wiring layers on a first wiring layer.
For making the multilevel embedded wiring system on the substrate, there has been proposed a method which comprises steps of: 1) forming a second insulating layer on a lower wiring embedded in a first insulating layer, 2) forming via-holes on the second insulating layer, 3) filling the via-holes with a conductive connecting material to make an interconnecting portion and 4) forming an upper wiring in a third insulating layer on the second insulating layer to connect the upper wiring to the lower wiring.
However, first it is necessary to make the via-holes in the second insulating layer by patterning the second layer through photolithography. In has been found that, an exposure light tends to make halation on a metal surface of the underlying wiring during the patterning process, resulting in poor accuracy of the via-hole formation and thus bad connection in some cases due to the underlying wiring having a narrow width.
Secondly, Cu materials are recommended to be used for the embedded wiring material because of having a high resistance to electromigration which causes disconnection of wiring and thus a short life of the fine wiring system, as well as a lower resistivity than that of Al. However, the second insulating layer on the lower embedded wiring is best formed by deposition of SiO
2
made by the conventional plasma-CVD method, in which the surface of the wiring is exposed to a high temperature oxygen atmosphere. It has been found that the Cu wiring surface is easily oxidized, resulting in high resistivity of the wiring. Further, because of easier diffusion of Cu than Al, it is necessary to prevent Cu diffusion into the insulating layer, reducing the insulation property and the device performance.
SUMMARY OF THE INVENTION
The present invention has been developed to overcome the above-described disadvantages, especially in case of using a Cu wiring material.
It is accordingly an objective of the present invention to provide a multilevel embedded wiring system structure for an IC provided with a conductive capping layer for preventing exposure light halation on a conductive layer during the patterning process.
Another objective of the present invention is to provide a multilevel embedded wiring system structure for an IC provided with a conductive capping layer for preventing conductive layer oxidation that results in an increased resistance of the wiring system and Cu diffusion that results in lowering of the insulation property of the insulating layer.
According to a first aspect of the present invention, there is provided a multilevel embedded wiring system structure for IC comprising channels for a first wiring system embedded in a first insulating layer formed on a substrate; a first conductive layer for a first wiring embedded in said trenches; a conductive capping layer embedded in the trenches for capping and connecting the first conductive layer and having an ability for preventing halation of an exposure light during a process of patterning a second insulating layer to be formed thereon; a second insulating layer formed over said first insulating layer and said conductive capping layer and provided with via-holes; a conductive connecting portion formed in said via-holes for connecting said conductive capping layer with a second conductive layer; a third insulating layer having trenches for a second wiring system; and a second conductive layer for a second wiring to be connected with said conductive connecting portion.
In case of the present multilevel embedded wiring system, there can be provided a flat surface on each wiring system which realize a more than triple embedded wiring system. Especially, the conductive capping layer on the conductive layer can prevent halation of an exposure light during a process of patterning a second insulating layer to be formed on the conductive capping layer, so that the via-holes and thus the conductive connecting portion can be prepared precisely.
In a preferred embodiment, Cu or its alloy (hereinafter referred to as the Cu material) may be used as a first conductive material. Comparing with Al material, the Cu material has a high resistance to electromigration and a low resistance, so that the conductive capping layer provided with an ability for preventing Cu diffusion can prevent Cu of the conductive layer from diffusing into the second insulating layer through the capping layer. Especially, in case of using the Cu material for wiring, trenches for the first and second wiring system should be provided with non-diffusion layers on side and bottom walls of the trenches to prevent the Cu diffusion into the insulating layer through the walls.
If an upper surface of the conductive layer is roughened, a good adherence between the conductive layer and the conductive capping layer can be obtained, resulting in advantages that there can be prevented peeling of the conductive capping layer during a CMP polishing process being applied thereon.
Further, the adherence of the capping layer can be improved by forming the capping layer in a way to get a larger contacting area between the capping layer and the conductive layer, such as a part of the capping layer enters into an upper part of the side walls of the trenches and encloses the top of the conductive material.
The conductive layer may be formed by a conventional Al or its alloy wiring material according to the present invention, because the capping layer on the conductive layer can prevent halation of the exposure light.
Preferably, the capping material may have non-oxidation property, because it can prevent oxidation of the first conductive layer during a process of forming a second insulating layer such as SiO
2
by means of CVD.
Examples of the conductive capping material may be selected from the group consisting of Ti, Ta, Mo, Cr, Al, W and their alloys, oxides, and nitrides.
According to an preferred embodiment of the present invention, there can be provided a multilevel embedded wiring system for IC wherein a second conductive capping layer is formed on the second conductive layer of the second wiring system, that is, a more than triple embedded wiring system for IC wherein a second connecting portion and a third conductive layer are formed on the second capping layer and so on.
In case of preparing the first and second conductive layer by the Cu material, it is recommendable to make the conductive capping layer by TiWN and make the conductive connecting portion by W or Cu.
In preparing a multilevel embedded wiring system, according to a second aspect of the present invention, there is provided a method of preparing a multilevel embedded wiring system for IC comprising 1) a first wiring formation step, 2) a first connecting portion formation step and 3) a second wiring formation step,
wherein 1) said first wiring formation step comprises steps of: forming trenches for a first embedded wiring in a first insulating layer on a substrate; and embedding in said trenches in turn a first conductive layer and a first conductive capping layer;
2) said first connecting portion formation step comprises steps of:
forming a second insulating layer over said first insulating layer and said first conductive capping layer; forming via-holes in a part of said second insulating l
Fukada Tetsuo
Hasegawa Makiko
Mori Takeshi
Toyoda Yoshihiko
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Wilczewski Mary
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