Method of making electrically programmable and erasable memory c

Details Method of making electrically programmable and erasable memory c Method of making electrically programmable and erasable memory c

1990-11-27

1992-03-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 48, 437 49, 437 50, 437 52, 437 61, 357 235, 357 236, H01L 21265

Patent

active

051008190

ABSTRACT:
First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60a , 60b) to control their conductance. A control gate conductor is insulatively disposed adjacent the control gate subchannel regions (62a, 62b) to control their conductance. In another embodiment, the field plate conductor (100) is replaced with a pair of field plate conductors (42a, 42b) that control the conductance of respective subchannel regions (64a, 64b). The field plate conductors (42a, 42b) act to self-align a diffused drain region (46) that replaces the inversion region (102).

REFERENCES:
patent: 4384349 (1983-05-01), McElroy
patent: 4558339 (1985-12-01), Angle
patent: 4608591 (1986-08-01), Ipri et al.
patent: 4736342 (1988-04-01), Imondi et al.

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