Method of making electrical connections to integrated circuit

Details Method of making electrical connections to integrated circuit Method of making electrical connections to integrated circuit

1998-04-29

2001-03-20

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S106000

Reexamination Certificate

active

06204164

ABSTRACT:

This invention relates to a method of making electrical connections to an integrated circuit (i.c.) chip.
Electrical connection between the chip circuitry and the integrated circuit package is most commonly accomplished by employing wire bonding techniques. For hermetic packages, the preferred technique is to ultrasonically bond aluminum wires to bonding pads on the i.c. chip, and for plastic packages, the preferred method is to form balls on gold wire and to use thermal compression to attach these balls to bonding pads on the integrated circuit.
Since the bonding wires are about 1 mil or larger diameter, the pad size has to be a few mils across to accommodate the bond. Signal wires leading form the bonding pad to the i.c. circuitry may be 0.5 &mgr;m wide, and are projected to continue to get smaller as technology improves.
More recently, techniques have been developed whereby the chip is attached face downwards on the substrate using tiny solder balls. This technique is used in ball grid arrays which allow a very high number of connections to be made to the i.c. A large pad is still required for the solder ball, however, and multiple layers of substrate interconnect may be needed to access the pads. Such a method is described in PCT patent application WO87/01509.
An object of the invention is to remove the limitation imposed by the large pad size needed for conventional assembly techniques (e.g. wire bonding, ball grid arrays or beam lead), and to provide a high conductivity path for heat to flow from the chip active area to the substrate.
Accordingly the present invention provides a method of making electrical connections to an integrated circuit chip, comprising the steps of providing at least one chip having exposed conductors on its active surface, providing a substrate having conductors on its surface corresponding to said exposed conductors on the chip, and mounting said at least one chip on said substrate so that said conductors are in accurate alignment with the corresponding conductors on the substrate, wherein a first oxide layer is formed on said active surface of said chip, a second oxide layer is formed on said surface of said substrate, said oxide layers are joined together by fusion bonding, and any voids between the conductors on the chip and the corresponding conductors on said substrate are filled with a conductive material.
One or a plurality of chips can be mounted on the substrate.
Fusion bonding is a technique by which two materials are bonded together by bringing their oxide covered surfaces together under temperature and pressure. The process produces a very strong bond. The system can be made to provide almost perfect thermal expansion matching between the two silicon components and the attachment layer, which is silicon dioxide in the case of silicon based technologies.
The method also provides an extremely low thermal path for heat dissipation from the chip to the substrate (approximately 0.03 deg C/Watt chip to substrate, and less than 1 deg C/Watt spreading resistance into the bulk substrate for a 1 cm square chip).
The electrical interconnection is made between narrow conductors on the chip and accurately aligned narrow conductors on the substrate. Both sets of conductors can be formed using i.c. photolithographic techniques, and chip to substrate alignment can be performed using through-the-chip infrared alignment techniques.
An important aspect of the invention the use of a fine gap between the chip conductor and the substrate conductor, which is subsequently bridged with a conductor. Bridging may be accomplished by capillary flow of a solder, or by surface wetting by a solder. Alternatively, a conductive plastic may be used to make the bridge.
The invention also provides an integrated circuit package comprising an integrated circuit having conductors on its active surface, a substrate having conductors on its surface corresponding to said exposed conductors on the chip, characterized in that a first oxide layer is present on said active surface of said integrated circuit, a second oxide layer is present on the surface of said substrate, said surfaces being joined together by fusion bonding of said oxide layers, and any voids between the conductors on the integrated circuit and the corresponding conductors on said substrate are filled with a conductive material.


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