Method of making EEPROM having coplanar on-insulator FET and con

Details Method of making EEPROM having coplanar on-insulator FET and con Method of making EEPROM having coplanar on-insulator FET and con

1997-06-24

1999-09-28

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438164, 438258, H01L 218247

Patent

active

059602651

ABSTRACT:
An EEPROM device is described incorporating a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

REFERENCES:
patent: 5188973 (1993-02-01), Omura et al.
patent: 5403762 (1995-04-01), Takemura
patent: 5411905 (1995-05-01), Acovic et al.
patent: 5437762 (1995-08-01), Ochiai

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