Method of making dRAM cell with trench capacitor

Details Method of making dRAM cell with trench capacitor Method of making dRAM cell with trench capacitor

1987-11-12

1989-01-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 48, 437203, 437162, 437919, H01L 2710, H01L 21302

Patent

active

047973730

ABSTRACT:
A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.

REFERENCES:
patent: 4105475 (1978-08-01), Jenne
patent: 4116720 (1978-09-01), Vinson
patent: 4199772 (1980-04-01), Natori et al.
patent: 4353086 (1982-10-01), Jaccodine et al.
patent: 4364074 (1982-12-01), Garnache et al.
patent: 4396930 (1983-08-01), Mizutani
patent: 4432006 (1984-02-01), Takei
patent: 4462040 (1984-07-01), Ho et al.
An Isolated-Merged Vertical Capacitor Cell for Large Capacity dRAM; Nakajima et al., IEDM, 1984, pp. 240-243.
Lee et al., "Short-Channel Field Effect Transistors in V-Grooves", IBM TDB, vol. 22, No. 8B, Jan. 1980, pp. 3630-3634.
Chang et al., "Fabrication of V-MOS or U-MOS Random Access Memory Cells with a Self Aligned Word Line", IBM TDB, vol. 22, Dec. 1979, pp. 2768-2771.
Barson, "Dynamic DMOS Random-Access Memory Cell Design With Trench", IBM TDB, vol. 21, No. 7, Dec. 1978, pp. 2755-2756.
Kenney, "V-Groove Dynamic Memory Cell", IBM TDB, vol. 23, No. 9, Feb. 1981, pp. 967-969.
Kenney, "Reduced Bit Line Capacitance in VMOS Devices", IBM TDB, vol. 23, No. 9, Feb. 1981, pp. 4052-4053.
Fatula et al, "N Skin Elimination in UMOS Device by Reoxidation", IBM TDB, vol. 22, No. 8A, Jan. 1980 pp. 3204-3205.
Chang, "Vertical FET Random-Access Memories with Deep Trench Isolation", IBM TDB, vol. 22, No. 8B, Jan. 1980, pp. 3683-3687.
"CMOS Dynamic Random-Access Memory Cell", IBM Tech. Disc. Bull., vol. 28-6 Nov. 1985, pp. 2578-2579.

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