Method of making devices having thin dielectric layers

Details Method of making devices having thin dielectric layers Method of making devices having thin dielectric layers

1999-07-12

2001-09-25

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S594000, C438S770000, C438S301000

Reexamination Certificate

active

06294447

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for making devices including semiconductor devices having thin dielectric layers and, in particular, to a process for growing dielectric layers that are ultra-thin and have improved quality.
BACKGROUND OF THE INVENTION
As microelectronic circuits become increasingly integrated, the demand for smaller components becomes stronger. The quest for miniaturization is particularly ardent with regard to transistors and memory devices such as dynamic random access memory (DRAM) cell structures. The metal-oxide semiconductor field-effect transistor (MOSFET or MOS device) is a dominant and important device in fabricating memory devices and integrated circuits, and various types of MOSFETS are known. MOSFET technology includes NMOS and CMOS technology, the former comprising n-channel MOS devices and the latter comprising n-channel and p-channel devices integrated on the same chip. Other acronyms are used to identify MOSFETs, including DMOS (wherein “D” stands for “diffusion” or “double diffusion”), PMOS (p-channel MOS), IGBT (Insulated Gate Bipolar Transistor), BiCMOS (CMOS having bipolar devices), and DGDMOS (Dual Gate DMOS). MOS devices may be integrated together or with other components or devices to form memory cells, such as DRAM cells, static random access memory (SRAM) cells, and flash electrically-programmable read-only memory (EPROM) cells.
A basic structural feature of transistors involves a dielectric or insulating layer. The migration of integrated circuits to smaller feature sizes is driving interest in developing thin film dielectrics and in particular, in producing dielectric layers that are thinner than 20 Å. As the cell size has shrunk, designers have attempted to produce such “ultra-thin” dielectric films, but processing constraints make it difficult to obtain uniform, high-quality reproducible dielectric films of this size. Typically, dielectric layers have been fabricated with a —SiO
x
, usually SiO
2
, although new materials for use in dielectrics are being developed having higher dielectric constants. See, e.g., U.S. Pat. No. 5,658,485 for “Pyrochlore Based Oxides With High Dielectric Constant And Low Temperature Coefficient,” and U.S. Pat. No. 5,552,355 for “Compensation of the Temperature Coefficient of the Dielectric Constant of Barium Strontium Titanate,” both of which are assigned to the present assignee.
Presently, there are two approaches which are most often used for growing thin film dielectric layers and particularly SiO
2
films, i.e., rapid thermal oxidation (RTO) and furnace oxidation. Both these approaches have limitations. Generally with RTO, a silicon substrate is oxidized with O
2
gas for a short period of time at high temperatures. Temperatures of about 1000° C. are used, and a radiant heater, such as a flashlamp heater apparatus, may be used to rapidly (e.g., within five minutes) produce the transition from a relatively low temperature (e.g., about 650° C.) to the oxidation temperature. The RTO equipment is not sufficiently robust for use in manufacturing processes, however, and the growth conditions may limit the potential for good properties at the Si—SiO
2
interface.
With furnace oxidation, typically wafers are held within a reaction tube and heated while gases are passed over them. Furnace oxidation processes generally operate at lower sacrificial dielectric layer, annealing the permanent layer in Argon or N
2
, and thereafter forming gate structures on the dielectric. This method has disadvantages in that it is restricted to formation of dielectrics with nitrogen-bearing species and requires a separate anneal step in which the substrate is subjected to temperatures of 500 to 950° C.
As may be appreciated, those involved in the field of semiconductors and in particular dielectric materials continue to seek to develop technologies for growing thin film dielectrics.
SUMMARY OF THE INVENTION
Summarily described, the invention comprises a method for making a thin dielectric layer for use in fabricating a semiconductor device, e.g., a transistor having a source, a drain, a channel running from source to the drain, a dielectric layer, and a gate electrode. The method of making the dielectric layer comprises a two-step process consisting of (i) growing a base layer of dielectric material on a substrate having a thickness in excess of the desired thickness for the layer, and (ii) etching back the base layer to the desired thickness. With this invention, it is not necessary that the dielectric layer be grown in the presence of a nitrogen ambient or that an anneal step be performed.


REFERENCES:
patent: 4552595 (1985-11-01), Hoga
patent: 4814291 (1989-03-01), Kim et al.
patent: 5670396 (1997-09-01), Shibib
patent: 5780342 (1998-07-01), Wang
patent: 5851888 (1998-12-01), Gardner et al.

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