Method of making connections to a semiconductor chip assembly

Metal working – Method of mechanical manufacture – Electrical device making

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

174 524, 257735, H01R 4300

Patent

active

059157526

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to methods, components and apparatus useful in mounting and connecting semiconductor devices.


BACKGROUND ART

Semiconductor chips typically are connected to external circuitry through contacts on a surface of the chip. The contacts on the chip typically are disposed in the regular patterns such as a grid substantially covering the front surface of the chip, commonly referred to as an "area array" or in elongated rows extending along each edge of the chip front surface. Each contact on the chip must be connected to external circuitry, such as the circuitry of a supporting substrate or circuit panel. Various processes for making these interconnections use prefabricated arrays of leads or discrete wires. For example, in a wirebonding process, the chip is physically mounted on the substrate. A fine wire is fed through a bonding tool. The tool is brought into engagement with the contact on the chip so as to bond the wire to the contact. The tool is then moved to a connection point of the circuit on the substrate, so that a small piece of wire is dispensed and formed into a lead, and connected to the substrate. This process is repeated for every contact on the chip.
In the so-called tape automated bonding or "TAB" process, a dielectric supporting tape, such as a thin foil of polyimide is provided with a hole slightly larger than the chip. An array of metallic leads is provided on one surface of the dielectric film. These leads extend inwardly from around the hole towards the edges of the hole. Each lead has an innermost end projecting inwardly, beyond the edge of the hole. The innermost ends of the leads are arranged side by side at spacing corresponding to the spacings of the contacts on the chip. The dielectric film is juxtaposed with the chip so that the hole is aligned with the chip and so that the innermost ends of the leads will extend over the front or contact bearing surface on the chip. The innermost ends of the leads are then bonded to the contacts of the chip, as by ultrasonic or thermocompression bonding. The outer ends of the leads are connected to external circuitry.
In a so-called "beam lead" process, the chip is provided with individual leads extending from contacts on the front surface of the chip outwardly beyond the edges of the chip. The chip is positioned on a substrate with the outermost ends of the individual leads protruding over contacts on the substrate. The leads are then engaged with the contacts and bonded thereto so as to connect the contacts on the chip with contacts on the substrate.
The rapid evolution of a semiconductor art in recent years has created a continued demand for progressively greater numbers of contacts and leads in a given amount of space. An individual chip may require hundreds or even thousands of contacts, all within the area of the chip front surface. For example, a complex semiconductor chip in current practice may have a row of contacts spaced apart from one another at center-to-center distances of 0.5 mm or less and, in some cases, 0.15 mm or less. These distances are expected to decrease progressively with continued progress in the art of semiconductor fabrication.
With such closely-spaced contacts, the leads connected to the chip contacts, must be extremely fine structures, typically less than 0.1 mm wide. Such fine structures are susceptible to damage and deformation. With closely spaced contacts, even minor deviation of a lead from its normal position will result in misalignment of the leads and contacts. Thus, a given lead may be out of alignment with the proper contact on the chip or substrate, or else it may be erroneously aligned with an adjacent contact. Either condition will yield a defective chip assembly. Errors of this nature materially reduce the yield of good devices and introduce defects into the product stream. These problems are particularly acute with those chips having relatively fine contact spacings and small distances between adjacent contacts.
It has been proposed to form a prefabricated

REFERENCES:
patent: 2758797 (1956-08-01), Miklau
patent: 3374537 (1968-03-01), Doelp, Jr.
patent: 3460105 (1969-08-01), Birt et al.
patent: 3517438 (1970-06-01), Johnson et al.
patent: 3684818 (1972-08-01), Netherwood
patent: 3822465 (1974-07-01), Frankort et al.
patent: 4030657 (1977-06-01), Scheffer
patent: 4069961 (1978-01-01), Nicklaus et al.
patent: 4141712 (1979-02-01), Rogers
patent: 4234666 (1980-11-01), Gursky
patent: 4312926 (1982-01-01), Burns
patent: 4320572 (1982-03-01), Bower et al.
patent: 4331740 (1982-05-01), Burns
patent: 4380042 (1983-04-01), Angelucci, Sr. et al.
patent: 4413404 (1983-11-01), Burns
patent: 4435741 (1984-03-01), Shimizu et al.
patent: 4616412 (1986-10-01), Schroeder
patent: 4633583 (1987-01-01), Kato
patent: 4756080 (1988-07-01), Thorp, Jr. et al.
patent: 4776509 (1988-10-01), Pitts et al.
patent: 4812421 (1989-03-01), Jung et al.
patent: 4859806 (1989-08-01), Smith
patent: 4887758 (1989-12-01), Suzuki et al.
patent: 4989069 (1991-01-01), Hawkins
patent: 5007576 (1991-04-01), Congleton et al.
patent: 5057461 (1991-10-01), Fritz
patent: 5059559 (1991-10-01), Takahashi et al.
patent: 5065504 (1991-11-01), Olla
patent: 5065506 (1991-11-01), Kiribayashi
patent: 5127570 (1992-07-01), Steitz et al.
patent: 5148265 (1992-09-01), Khandros et al.
patent: 5148266 (1992-09-01), Khandros et al.
patent: 5148967 (1992-09-01), Gabaldon et al.
patent: 5156318 (1992-10-01), Suzuki et al.
patent: 5173574 (1992-12-01), Kraus
patent: 5177863 (1993-01-01), Lam
patent: 5189363 (1993-02-01), Bregman et al.
patent: 5193732 (1993-03-01), Interrane et al.
patent: 5217154 (1993-06-01), Elwood et al.
patent: 5225633 (1993-07-01), Wigginton
patent: 5252784 (1993-10-01), Asai et al.
patent: 5390844 (1995-02-01), DiStefano et al.
patent: 5398863 (1995-03-01), Grube et al.
patent: 5477611 (1995-12-01), Sweis et al.
patent: 5489749 (1996-02-01), DiStefano et al.
patent: 5491302 (1996-02-01), DiStefano et al.
patent: 5536909 (1996-07-01), DiStefano et al.
patent: 5548091 (1996-08-01), DiStefano et al.
patent: 5550406 (1996-08-01), McCormick
patent: 5552631 (1996-09-01), McCormick
patent: 5619017 (1997-04-01), DiStefano et al.
patent: 5629239 (1997-05-01), DiStefano et al.
patent: 5638596 (1997-06-01), McCormick
patent: 5706174 (1998-01-01), DiStefano et al.
"Recent Advances In Single Point Tab Bonding Tools", by Jerry Carlson, Microminiature Technology, Inc. ** (Oct. 23, 1990).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of making connections to a semiconductor chip assembly does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making connections to a semiconductor chip assembly, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making connections to a semiconductor chip assembly will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1369175

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.