Method of making conductive paths through a lamina in a semicond

Details Method of making conductive paths through a lamina in a semicond Method of making conductive paths through a lamina in a semicond

1981-10-19

1983-03-29

Smith, John D.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

156643, 156644, 204192E, 427 88, 427259, 427 91, 427 99, 430314, H01L 21285

Patent

active

043783830

ABSTRACT:
On the layer 12 a mask 3 corresponding to the desired pattern of holes 15 is provided with via openings 14 having overhanging walls. The layer 12 is selectively etched with a method where the etching attack takes place vertically to the layer surface, and wherein the mask 3 is thinned simultaneously, so that holes 15 are obtained having a cross-section increasing toward the mask 3. If subsequently material 16 for filling the holes 15 is applied in a blanket deposition these holes are completely filled when the material 16 has the same thickness as the layer 12 although the openings over the holes are decreasing with increasing thickness of the material 16. The layer 12 consists preferably of an insulation material, the mask 3 of positive photoresist, and the material 16 of a metal.

REFERENCES:
patent: 3767490 (1973-10-01), Alberts
patent: 4076575 (1978-02-01), Chang
patent: 4108717 (1978-08-01), Widmann
Ephrath, "Selective Etching of Silicon Dioxide Using Reactive Etching with CF.sub.4 -H.sub.2 ", J. Electrochem. Soc., vol. 126, No. 8, Aug. 1979.
Chiu et al., "Ion Etch Lift Off Process", IBM TDB, vol. 19, No. 9, pp. 3409-3410, Feb. 1977.
Winter, "Metal Deposition with Polyimide Lift-Off Technique", IBM TDB, vol. 17, No. 5, Oct. 1974.

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