Method of making capacitors

Details Method of making capacitors Method of making capacitors

2003-01-30

2003-09-09

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000

Reexamination Certificate

active

06617221

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates to a method for manufacturing capacitors and, in particular, to a manufacturing method for a capacitor whose upper electrode area is smaller than the lower electrode area. A hard mask is inserted between the conventional upper electrode metal and the photo resist layer. This enables one to perform the in-situ photo resist layer removal step after dry etching the upper electrode metal.
2. Related Art
Among the existing very large-scale integrated (VLSI) circuits, the capacitor is one of the most commonly used passive elements. It is often integrated into active elements such as bipolar transistors or complementary metal oxide semiconductor (CMOS) transistors. These capacitors usually have the forms of polysilicon-insulator-polysilicon (PIP), metal-insulator-silicon (MIS), metal-insulator-metal (MIM), and metal-insulator-polysilicon (MIP).
With reference to
FIGS. 1A through 1E
, the MIP capacitor is featured in that its upper electrode area is smaller than the lower electrode area (the capacitance is defined by the upper electrode). This conventional manufacturing method includes the following steps. First, as shown in
FIG. 1A
, a substrate
10
such as a silicon wafer is provided. Then a lower electrode polysilicon
20
is formed to cover part of the substrate
10
. Afterwards, a dielectric layer
30
is formed to cover the lower electrode polysilicon
20
and part of the substrate
10
. An inter layer dielectric (ILD)
40
is formed to cover the dielectric layer
30
, except for the part that covers the lower electrode polysilicon
20
. An upper electrode metal
50
is formed to cover the ILD
40
and part of the dielectric layer
30
on the lower electrode polysilicon
20
. The upper electrode metal
50
has an opening
60
above the lower electrode polysilicon
20
.
As shown in
FIG. 1B
, a photo resist layer
70
is formed to cover the opening
60
of the upper electrode metal
50
. Afterwards, the upper electrode metal
50
is dry etched with the photo resist layer as the mask, By appropriately controlling the etching time, the dielectric layer
30
can be protected from being etched. The upper electrode metal
52
, the opening
100
, and several metal blocks
80
are thus formed, as shown in FIG.
1
C. The metal blocks
80
are formed at the bottom of the opening
100
as a result of imperfect dry etching.
The photo resist layer
70
is further used as the mask to perform wet etching to completely remove the metal blocks
80
. As the wet etching is Isotropic, the upper electrode metal
52
is also etched, forming the arc side wall
90
shown in FIG.
1
D. Afterwards, the photo resist layer
70
is removed to form the capacitor structure shown in FIG.
1
E.
In the above-mentioned conventional capacitor manufacturing method, one has to properly control the etching time such that the dry etching does not penetrate through the dielectric layer
30
to damage the lower electrode polysilicon
20
. However, this results in incomplete etching and leaves metal blocks
80
. In fact, even if one extends the etching time to etch through the dielectric layer
30
and damage the lower electrode polysilicon
20
, there will still be a few metal blocks
80
produced. In order to completely remove the metal blocks
80
after dry etching, the wet etching process is necessary. However, in order to protect the upper electrode metal
52
from seriously etched by the wet etchant, the step of removing the photo resist layer
70
is delayed until the wet etching is over. This further results in a problem. That is, if the Q-time between the end of the dry etching and the beginning of the wet etching is too long, the upper electrode metal
52
will be seriously corroded as it is exposed to the atmosphere.
SUMMARY OF THE INVENTION
In view of the foregoing, an objective of the invention is to provide a method for manufacturing capacitors to solve the problem of corrosion occurring to the upper electrode metal.
Another objective of the invention is to provide a method for manufacturing capacitors to prevent the lower electrode polysilicon from being corroded by the wet etchant.
According to the above objectives, the disclosed method is applicable to capacitors with an upper electrode smaller than the lower electrode in area. The method includes the following steps. First, a substrate is provided. A lower electrode polysilicon is formed to cover part of the substrate. A dielectric layer is formed to cover the lower electrode polysilicon and part of the substrate. An inter layer dielectric (ILD) is formed to cover the dielectric layer, except for the part that covers the lower electrode polysilicon. An upper electrode layer is formed to cover the ILD and part of the dielectric layer above the lower electrode polysilicon. The upper electrode layer has a first opening on top of the lower electrode polysilicon. Afterwards, a hard mask is formed to cover the upper electrode layer. A photo resist layer covers the hard mask in the first opening. The photo resist layer is used as the mask to dry etch part of the hard mask, part of the upper electrode metal, and part of the dielectric layer, forming a second opening and some metal blocks and exposing part of the lower electrode polysilicon. The metal blocks are formed at the bottom of the second opening. The photo resist layer is then removed to form an oxide layer on the exposed lower electrode polysilicon. The hard mask is used as the mask to perform wet etching for removing the metal blocks. Finally, the hard mask is removed.


REFERENCES:
patent: 6274435 (2001-08-01), Chen

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