Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-03-29
1999-11-02
Celsa, Bennett
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438655, 438660, 438661, 438672, 438675, 438357FOR, 438358FOR, H01L 21283
Patent
active
059769700
ABSTRACT:
A method of forming electrical conductors having sub-half-micron geometries and using a high yield process is described. Trenches provided with an overhang are positioned where a metal interconnection is to be formed. A composite insulator layer is deposited and is followed by laterally filling with metal the trench under the overhang. Excess metal is then chem-mech polished. Only the non-crucial neck of the metal wiring is left exposed during polishing. Since spacing between the exposed metal lines is increased, it requires longer distances for the metal to smear and cause unwanted shorts. Three methods are described to laterally fill the trenches under the overhang. A first method describes the process parameters to achieve lateral deposition by high surface mobility and low sticking coefficient. A second method teaches a technique of inducing micro-creep to laterally fill the trenches under the overhang. A third method shows metal layered structures where volume expansion takes place upon phase transformation.
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W. M. Moreau, "Semiconductor Lithography--Principles, Practices, and Materials" MICRODEVICES, Physics and Fabrication Technologies, 1988, pp. 631-673.
JAPIO AN 95-058199 of JP 07-058-199.
WPIDS AN 95-134 781 of JP 07-058-199.
Dalal Hormazdyar Minocher
Rathore Hazara Singh
Celsa Bennett
International Business Machines - Corporation
Schnurmann H. Daniel
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