Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
1999-04-07
2001-03-27
Kelly, C. H. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S319000, C430S320000
Reexamination Certificate
active
06207354
ABSTRACT:
TECHNICAL FIELD
The invention pertains generally to circuitized substrates and particularly to chip carriers for integrated circuits (semiconductor chips).
CROSS-REFERENCE TO COPENDING APPLICATIONS AND PATENTS
In Ser. No. (S.N.) 08/495,248, now U.S. Pat. No. 5,599,747, entitled “Method Of Making Circuitized Substrate” and filed Jun. 27, 1995, there is defined a process for making a circuitized substrate wherein a temporary support portion is formed and removed, leaving at least of the formed cavity's sidewalls not including metallization thereon following the removal.
In Ser. No. 08/359,491, now U.S. Pat. No. 5,542,175, entitled “Method Of Laminating And Circuitizing Substrates Having Openings Therein” and filed Dec. 20, 1994, there is defined a method of laminating two substrates and circuitizing at least one of these. A plug is provided and shaped to fit within an opening defined in the structure, and then removed following lamination and circuitization.
In Ser. No. 08/390,344, now U.S. Pat. No. 5,798,909, entitled “Organic Chip Carriers For Wire Bond-Type Chips” and filed Feb. 15, 1995, there is defined a chip carrier having a single-tiered cavity within a dual layered (of organic material) substrate and a semiconductor chip located in the cavity. The chip is wire bonded to circuitry on the substrate.
In Ser. No. 08/470,389, now U.S. Pat. No. 5,566,448, entitled “Method Of Construction Of Multi-Tiered Cavities Used In Laminate Carriers”, filed Jun. 6, 1995, there is defined a method of forming a chip module wherein a rigid cap and substrate are used, the cap and substrate laminated together with bond pads connected to circuitry disposed in a bottomed cavity of the cap. Following cap circuitization, part of the cap (that over the cavity) is removed and a semiconductor chip coupled to the circuitry.
In Ser. No. 08/820,995, filed Mar. 20, 1997 and entitled “Method Of Making A Circuitized Substrate”, there is defined a method of making a circuitized substrate using a removable film layer. Ser. No. 08/820,995 is now U.S. Pat. No. 5,953,594, having issued Sep. 14, 1999.
In Ser. No. 09/042,898, filed Mar. 17, 1998 and entitled “Method Of Making An Enhanced Organic Chip Carrier Package”, there is defined another method of making a circuitized substrate using a removable film layer.
It is understood that the presently claimed invention represents an alternative, enhanced version of the methods in Ser. No. 08/820,995 and Ser. No. 09/042,898.
The above pending application and patents are assigned to the same assignee as the present invention. The teachings of these documents are incorporated herein by reference.
BACKGROUND OF THE INVENTION
It is known that integrated circuit devices (hereinafter referred to as semiconductor chips) are typically electronically packaged by mounting one or more chips onto a dielectric, e.g., alumina, circuitized substrate (referred to as a chip carrier), with wire bonds used to electrically connect I/O (input/output) contact pads on each chip to corresponding contact pads (and therefore to corresponding fan-out circuitry) on the circuitized chip carrier substrate. Wire bonding is a well known process in the art and further description is not believed necessary. The resulting chip carrier is then typically mounted on a printed circuit board (PCB) and, using circuitry on the PCB, electrically coupled to other such chip carriers and/or other electronic components mounted on the PCB.
Ceramic chip carrier structures have proven extremely useful in the electronic packaging field. However, the use of ceramic as the dielectric material of the substrate does present certain limitations and drawbacks. For example, the speed of propagation of an electrical signal through a conductive wire located on a dielectric layer (or between two dielectric layers for that matter) is proportional to the inverse of the square root of the dielectric constant of the dielectric material layer or layers. As is known, the dielectric constants of most ceramics are relatively large, e.g., the dielectric constant of alumina (the primary constituent of ceramic materials used in these substrates) is relatively high, which results in ceramic chip carriers exhibiting relatively low signal propagation speeds in comparison to substrates of other (e.g., organic) materials, such as fiberglass-reinforced epoxy resin, polytetrafluoroethylene, etc.
Ceramic chip carrier usage also presents certain input/output (I/O) constraints. For example, a single-layer ceramic chip carrier substrate includes but a single layer of fan-out circuitry on the upper surface of the ceramic substrate, extending to contact pads around the outer periphery of the substrate. A lead frame, having inner leads connected to these peripheral contact pads, is typically used to electrically connect such a ceramic chip carrier to a printed circuit board (PCB). As the number of chip I/Os has increased (in response to more recent enhanced design requirements), it has been necessary to increase the wiring density, sometimes to the point where undesirable cross-talk between adjacent wires may occur. Further, it has become increasingly difficult to form a correspondingly large number of contact pads around the outer periphery of the ceramic substrate. Accordingly, it is understood that single-layer ceramic chip carrier substrates are limited in the ability thereof to accommodate semiconductor chips with significantly increased I/O counts as required in today's packaging designs.
Efforts to accommodate semiconductor chips having relatively large numbers of I/O pads have led to the use of multilayer ceramic chip carrier substrates utilizing what are referred to as “ball grid arrays” (BGAs) in lieu of lead frames. Such multilayer types of ceramic chip carrier substrates differ from single-layer ceramic chip carrier substrates in that these include two or more layers of fan-out circuitry on two or more ceramic layers. Significantly, these layers of fan-out circuitry are electrically interconnected by mechanically drilled holes (called “vias”), which are plated and/or filled with electrically conductive material (e.g., copper). In addition, a certain number of such holes extend from the layers of fan-out circuitry to respective lands on the chip carrier substrates, on which are mounted solder balls (formed in grid arrays, hence the term “ball grid array”). These solder balls are intended to be mechanically and electrically connected to corresponding solderable contact pads on a receiving substrate, e.g., PCB. Unfortunately, the mechanically drilled holes electrically interconnecting the layers of fan-out circuitry have relatively large diameters, requiring the spacing between the fan-out wires to be relatively large. This relatively large spacing between fan-out wires understandably limits the number of chip I/O pads which can be accommodated.
Additional efforts to package chips having a relatively large number of chip I/O pads have led to the use of multi-tiered cavities in multi-layered ceramic substrates. When using such a packaging configuration, a chip is mounted face-up (its I/O pads facing upwardly) at the bottom of a multi-tiered cavity. Wire bonds (e.g., using fine gold wire) are extended from the I/O contact pads on the exposed upper surface of the chip to respective contact pads on the exposed upper surfaces of the different layers of the multi-layered ceramic substrate. While this configuration does make it possible to accommodate a relatively large number of chip I/O pads, it unfortunately typically mandates usage of multiple manufacturing set-up operations to accommodate the different tier height for the relatively long wire bonds extending from the chip to the spaced tiers.
Typically, ceramic chip carrier substrates are also limited in heat dissipation capabilities. For example, in the case of a multilayer ceramic chip carrier having a chip positioned at the bottom of a multi-tiered cavity, heat dissipation is typically achieved by providing a heat sink directly beneath the cavity. This implies, however, that the h
Bhatt Anilkumar C.
Miller Thomas R.
Moring Allen F.
Walsh James P.
Fraley Lawrence R.
International Business Machines Coporation
Kelly C. H.
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