Method of making an integrated circuit structure with planarized

Details Method of making an integrated circuit structure with planarized Method of making an integrated circuit structure with planarized

1996-06-19

1999-11-16

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438671, 438696, 438720, 438725, 438738, 438742, H01L 2144

Patent

active

059857617

ABSTRACT:
An integrated circuit structure includes a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.

REFERENCES:
patent: 4818715 (1989-04-01), Chao
patent: 5003062 (1991-03-01), Yen
patent: 5061647 (1991-10-01), Roth et al.
patent: 5210435 (1993-05-01), Roth et al.
patent: 5317192 (1994-05-01), Chen et al.
patent: 5368686 (1994-11-01), Tatsumi et al.
patent: 5479054 (1995-12-01), Tottori
patent: 5502324 (1996-03-01), Hachisuka et al.
patent: 5505322 (1996-04-01), Shinohara et al.
patent: 5569627 (1996-10-01), Shinohara et al.
patent: 5578163 (1996-11-01), Yachi
patent: 5599743 (1997-02-01), Nakagawa et al.
patent: 5679213 (1997-10-01), Noshiro
patent: 5741742 (1998-04-01), Kamide
patent: 5767018 (1998-06-01), Bell
patent: 5772906 (1998-06-01), Abraham
Wolf et al., Silicon Processing For The VLSI era, vol. l, Lattice Press, 1986, pp. 545-557.

Affiliated with

Also associated with

Rating

Method of making an integrated circuit structure with planarized does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making an integrated circuit structure with planarized, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making an integrated circuit structure with planarized will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1324377