Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Patent
1998-05-26
1999-09-07
Picardat, Kevin M.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
438118, 438125, H01L 2144
Patent
active
059500743
ABSTRACT:
A package for an integrated circuit is described, as is a method of making the package. An exemplary method of making a package for an integrated circuit die includes a first step of providing an insulating substrate having a substantially planar first surface. A conductive path extends through the substrate. Step two of the method places an integrated circuit die, such as an EEPROM or a CCD or SAW integrated circuit die, on the first surface of the substrate. Step three electrically connects the integrated circuit die to the conductive path. Step three applies an imperforate bead of a viscous adhesive material on the first surface of the substrate around the die. The bead extends to a height above the first surface of the substrate greater than the height of the integrated circuit die. Step four provides a lid having a first surface. Step five places a peripheral portion of the first surface of the lid on the bead, such that the first surface of the lid is above the first surface of the substrate and the integrated circuit die. Step six press fits the lid into the bead. Step seven hardens the bead, and thus completes the package. Epoxy is a preferred material for the bead. The lid is a single-piece of flat material, such as plastic, ceramic, or glass, which can have a diagonal edge.
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Glenn Thomas P.
Hollaway Roy D.
Panczak Anthony E.
Amkor Technology Inc.
MacPherson Alan H.
Parsons James E.
Picardat Kevin M.
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