Method of making a three-dimensional memory cell with integral s

Details Method of making a three-dimensional memory cell with integral s Method of making a three-dimensional memory cell with integral s

1990-06-22

1991-09-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 38, 437 51, 437 52, 437191, 437193, 437228, 437233, 437235, H01L 2170

Patent

active

050495151

ABSTRACT:
A three-dimensional floating gate memory cell including an integral select gate transistor is disclosed. Source and drain are formed in a silicon substrate wherein the drain is formed under a slot which has been etched into the body of the substrate. In this way, the channel defined between the source and drain has both horizontal and vertical regions. The cell also includes a floating gate, which is completely surrounded with insulation, and a control gate which is insulated above and extends over the floating gate. The control gate is also insulated above and extends over the vertical portion of the channel within the slot. This allows the second gate member to regulate the current flowing in the vertical portion of the channel; that is, the second gate member and the vertical channel section form an integral select device.

REFERENCES:
patent: 4222062 (1980-09-01), Trotte et al.
patent: 4713677 (1987-12-01), Tigebar et al.
patent: 4796228 (1989-01-01), Bagbe
patent: 4814840 (1989-03-01), Kameda

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