Method of making a thick microstructural oxide layer

Details Method of making a thick microstructural oxide layer Method of making a thick microstructural oxide layer

2005-11-08

2005-11-08

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Physical stress responsive

C438S050000, C438S051000, C438S053000

Reexamination Certificate

active

06962831

ABSTRACT:
A method of fabricating a thick silicon dioxide layer without the need for long deposition or oxidation and a device having such a layer are provided. Deep reactive ion etching (DRIE) is used to create high-aspect ratio openings or trenches and microstructures or silicon pillars, which are then oxidized and/or refilled with LPCVD oxide or other deposited silicon oxide films to create layers as thick as the DRIE etched depth allows. Thickness in the range of 10-100 μm have been achieved. Periodic stiffeners perpendicular to the direction of the trenches are used to provide support for the pillars during oxidation. The resulting SiO2layer is impermeable and can sustain large pressure difference. Thermal tests show that such thick silicon dioxide diaphragms or layers can effectively thermally isolate heated structures from neighboring structures and devices within a distance of hundred of microns. Such SiO2diaphragms or layers of thickness 50-60 μm can sustain an extrinsic shear stress up to 3-5 Mpa. These thick insulating microstructures or layers can be used in thermal, mechanical, fluidic, optical, and bio microsystems.

REFERENCES:
patent: 4211582 (1980-07-01), Horng et al.
patent: 6461888 (2002-10-01), Sridhar et al.
patent: 2001/0013630 (2001-08-01), Cho et al.
patent: 0 996 149 (2000-04-01), None
patent: 11051893 (1999-02-01), None
Rossi, Carole, et al., Realization, Characterization of Micro Pyrotechnic Actuators and FEM Modelling of the Combustion Ignition, 1998 Elsevier Science S.A., 70, pp. 141-147.
Cai, Jun, et al., A Partial SOI Technology For Single-Chip RF Power Amplifiers, International Electron Devices Meeting 2001, IEDM Technical Digest, Washington, D.C., Dec. 2-5, 2001, New York, NY: IEEE, U.S. Dec. 2, 2001, pp. 891-894.
Kugimiya, K., et al., 101-stage 2 μm Gate Ring Oscillators In Laser-Grown Silicon, Islands Embedded in SiO2, 8179 IEE Electron Devices Leters, vol. EDL-3, No. 9, New York, Sep. 1982.
Lehmann, V., Porous Silicon—A New Material For MEMS, MEMS 1996, Munchen, Germany, pp. 1-6.
Nam, Choong-Mo, et al., Selective Oxidized Porous Silicon (SOPS) Substrate for Microwave Power Chip-Packaging, Electrical Performance of Electronic Packaging, IEEE 5thTopical Meeting, 1996, pp. 202-204.
Haiyan, Ou, et al., Thick SiO2Layer Produced By Anodisation, Electronics Letters, V35, 1999, pp. 1950-1951.

Affiliated with

Also associated with

Rating

Method of making a thick microstructural oxide layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making a thick microstructural oxide layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a thick microstructural oxide layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3512124