Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-04-30
2004-07-27
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S713000, C438S718000, C438S719000, C438S721000, C438S741000
Reexamination Certificate
active
06767835
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of making a shaped gate electrode structure, and a device comprising same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
FIG. 1
depicts an example of an illustrative transistor
10
fabricated on a wafer or substrateI
11
. The transistor
10
is comprised of a gate insulation layer
14
, a gate electrode
16
, sidewall spacers
19
, a drain region
18
A, and an source region
18
B. Trench isolation regions
17
are formed in the substrate
11
. Also depicted in
FIG. 1
are a plurality of conductive contacts
15
formed in a layer of insulating material
21
. The conductive contacts
15
provide electrical connection to the drain and source regions
18
A,
18
B. As constructed, the transistor
10
defines a channel region
12
in the substrate
11
beneath the gate insulating layer
14
. The substrate
11
is normally doped with an appropriate dopant material, i.e., a P-type dopant such as boron or boron difluoride for NMOS devices, or an N-type dopant such as arsenic or phosphorous for PMOS devices.
As the critical dimension of transistors have continued to decrease, the distance between the drain and source regions
18
A,
18
B may not, in some cases, be the limiting factor in terms of the device performance. Typically, the gate electrode
16
depicted in
FIG. 1
has a longitudinal dimension, i.e., a dimension into the page, that extends up to approximately 20 &mgr;m whereas the critical dimension
16
A of the gate electrode
16
may be as small as 70-180 nm, and further reductions are planned in the future. In general, the gate electrode
16
is used to establish a transverse electric field to activate the transistor
10
. Since the gate electrode
16
is typically contacted at only one end, the electrical charges used to establish the electrical field have to be transported along the entire longitudinal length of the gate electrode
16
to uniformly build up the transverse electrical field. Given the small critical dimension
16
A of the gate electrode
16
, which is usually comprised of polycrystalline silicon, the electrical resistance of the gate electrode
16
is relatively high which tends to result in relatively high RC-delay time constants. As a result, the development of the transverse electrical field necessary to fuilly open the channel region
12
is delayed, thereby deteriorating the switching speed of the transistor
10
. As a consequence, the rise and fall times of the electrical signals are increased and the operating frequency, i.e., the clock frequency, is decreased. Thus, the operating speed or switching time of field effect transistors may no longer be limited by the length of the channel region
12
, but may depend, at least to some degree, upon the delay in signal propagation along the longitudinal length of the gate electrode
16
.
Additionally, the drive to reduce the critical dimension
16
A of the gate electrode
16
to smaller sizes is limited, at least to some degree, by the ability of photolithography tools to accurately pattern the feature, i.e., the gate electrode
16
, to the desired size or critical dimension
16
A. Although efforts are continually being made to improve the ability of photolithography tools, techniques and systems to reduce the critical dimensions of features formed on an integrated circuit device, such efforts may not be successful for a number of years, if at all. Thus, a need exists for forming features, such as the gate electrode
16
depicted in
FIG. 1
, with a critical dimension
16
A that may be less than a size which may be directly formed using existing photolithography tools, methods and systems.
The present invention is directed to various methods and a device that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is generally directed to a method of making a shaped gate electrode structure, and a device comprising same. In one illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a layer of polysilicon above the gate insulation layer, implanting a dopant material into the layer of polysilicon, forming an undoped layer of polysilicon above the doped layer of polysilicon and performing an etching process on the undoped layer of polysilicon and the doped layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode. In further embodiments, the method comprises forming a layer of refractory metal above the gate electrode and performing at least one heating process to form a metal silicide region on the gate electrode structure.
In another illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a first layer of polysilicon above the gate insulation layer, implanting a dopant material into the first layer of polysilicon to form a doped region having a dopant concentration level in the layer of polysilicon, forming a second layer of polysilicon above the doped region of the first layer of polysilicon, the second layer of polysilicon having a dopant concentration level that is less than the dopant concentration level of the doped region in the first layer of polysilicon, and performing an etching process on the second layer of polysilicon and the doped region in the first layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode.
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Goto et al., “Optimization of Salicide Processes for sub 0.1-&mgr;m CMOS Devices,”1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 119-120, Apr. 1994.
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Brown David E.
Nariman Homi E.
Advanced Micro Devices , Inc.
Norton Nadine G.
Tran Binh X.
Williams Morgan & Amerson P.C.
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