Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-09-29
2002-04-02
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S014000, C438S017000, C438S018000, C438S142000, C438S459000, C438S606000, C438S637000, C438S639000, C438S666000
Reexamination Certificate
active
06365513
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an electronic device used for a mobile communication unit or the like in the field of information/telecommunication technology and a method for fabricating the same.
In recent years, demand for various types of mobile communication units such as cellular phones and personal handy phone systems (PHS) has tremendously increased. In order to catch up with such rapidly increasing demand, the frequencies applied to these mobile communication units have exceeded the MHz bands to reach the GHz bands. In a frequency converter or a signal amplifier for the receiver or transmitter section of such a mobile communication unit, a gallium arsenide (GaAs) field effect transistor (FET), which can operate with high gain, low distortion and small current even in a high frequency region, is widely used.
A large number of GaAs FETs are formed on a semi-insulating substrate made of GaAs. Then, during mounting, the substrate is divided by dicing into respective chips. Each of the divided chips is mounted on a lead frame. Thereafter, the electrodes of each GaAs FET are electrically connected to the lead frame via an Au wire.
However, if an FET having such a structure is operated in a high frequency region, then the gain of the FET adversely decreases, because the Au wire contributes to the formation of parasitic inductance.
Thus, in order to solve this problem, a method for electrically connecting the electrodes of an FET formed on a GaAs substrate to a lead frame through a conductor layer filled in a via hole formed in the GaAs substrate is suggested in Japanese Laid-Open Publication No. 6-5880, for example. In accordance with this method, the distance between the electrodes of the FET and the lead frame to be connected thereto can be shortened compared with connecting the electrodes to the lead frame via an Au wire. As a result, the parasitic inductance can be considerably reduced and the decrease in gain of the FET can be prevented.
Hereinafter, a conventional method for fabricating an electronic device having a via hole as disclosed in Japanese Laid-Open Publication No. 6-5880 will be described with reference to FIGS.
12
(
a
) through
12
(
d
).
First, as shown in FIG.
12
(
a
), an FET, including an active layer
12
, a source electrode
13
, a drain electrode
14
and a gate electrode
15
, is formed on the principal surface of a substrate
11
made of GaAs and having a thickness of 600 &mgr;m. Then, as shown in FIG.
12
(
b
), the back surface of the substrate
11
is polished to have the thickness thereof reduced to several tens to one hundred and several tens &mgr;m.
Next, as shown in FIG.
12
(
c
), an etching mask
16
having an opening
16
a
at a site corresponding to the source electrode
13
is formed on the back surface of the substrate
11
, and the substrate
11
is etched using this mask
16
, thereby forming a via hole
17
in the substrate
11
so as to reach the back surface of the source electrode
13
.
Subsequently, as shown in FIG.
12
(
d
), the etching mask
16
is removed, and a plating undercoat layer
18
is formed over the entire back surface of the substrate
11
as well as the wall and bottom surfaces of the via hole
17
. Then, a metal electrode
19
is formed over the plating undercoat layer
18
by electroplating technique such that the via hole
17
is filled in with the metal electrode
19
. In this manner, an electronic device, which includes the substrate
11
with a reduced thickness and in which the source electrode
13
is electrically connected to the metal electrode
19
, can be obtained. It is noted that the plating undercoat layer
18
improves the adhesion of the metal electrode
19
to the substrate
11
.
However, in accordance with this conventional method for fabricating an electronic device, since the via hole
17
is formed by etching the thinned substrate
11
using the etching mask
16
, the substrate
11
is likely to crack. The reason is as follows. In order to form the via hole
17
, the thinned substrate
11
must be transported to an apparatus for forming the etching mask
16
and then to an apparatus for etching the substrate
11
. That is to say, since the substrate
11
, which has the mechanical strength thereof decreased because of the reduction in thickness thereof, should be transported to these apparatuses, the substrate
11
is more likely to crack during the transportation. Thus, in accordance with the conventional method for fabricating an electronic device, the production yield adversely decreases.
Also, in order to form the via hole
17
in the substrate
11
, the etching mask
16
having the opening
16
a
at the site corresponding to the source electrode
13
should be formed over the back surface of the substrate
11
. Accordingly, during this process step, the position of the source electrode
13
formed on the principal surface of the substrate
11
should be aligned with the position of the opening
16
a
of the etching mask
16
formed on the back surface of the substrate
11
. However, in order to align the position of the source electrode
13
on the principal surface of the substrate
11
with the position of the opening
16
a
of the etching mask
16
on the back surface thereof, a special aligner must be used. In addition, the process step required is adversely complicated and difficult.
SUMMARY OF THE INVENTION
In view of the above-described problems, the objects of the present invention are to prevent a decrease in production yield because of cracking of a substrate during the transportation step for forming a via hole in the substrate, and to eliminate a complicated alignment step conventionally required for forming a via hole in the substrate.
In order to accomplish these objects, a first method for fabricating an electronic device according to the present invention includes the steps of: a) forming a via hole in the principal surface of a substrate, the via hole having a bottom; b) forming a conductor layer at least over a sidewall of the via hole; and c) thinning the substrate by removing a portion of the substrate such that the conductor layer is exposed, the portion of the substrate being opposite to another portion of the substrate in which the via hole is formed.
In accordance with the first method for fabricating an electronic device, a via hole having a bottom is formed in the principal surface of a substrate, a conductor layer is formed at least over a sidewall of the via hole, and then the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed. Thus, the steps of forming the via hole in the substrate and forming the conductor layer in the via hole can be performed on a substrate that has not been thinned yet and thus still retains a sufficient mechanical strength. Accordingly, the step of transporting a thinned substrate to an apparatus for forming a via hole or to an apparatus for forming a conductor layer need not be performed. As a result, it is possible to prevent the substrate from cracking during the transportation of the substrate to these apparatuses and the production yield of the electronic device can be increased as compared with a conventional method.
In addition, no etching mask for forming a via hole needs to be formed over the back surface opposite to the principal surface of the substrate. Thus, a complicated alignment step using a special aligner, which has been required by a conventional method for aligning the position of an opening of the etching mask formed on the back surface of the substrate with the position of an electrode layer formed on the principal surface of the substrate, is no longer necessary.
In one embodiment of the present invention, the method preferably further includes, prior to the step a), the step of d) forming an electrode layer on the principal surface of the substrate, the electrode layer having a through hole over a region where the via hole is to be formed. The step a) prefe
Furukawa Hidetoshi
Ishida Hidetoshi
Noma Atsushi
Tanaka Tsuyoshi
Ueda Daisuke
Nguyen Ha Tran
Robinson Eric J.
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