Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1995-11-07
1999-08-31
Tsai, Jey
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438646, 438698, 438253, H01L 214763
Patent
active
059465913
ABSTRACT:
A manufacturing method for semiconductor devices such as dynamic RAM, etc. which removes the layer part more on the high position than an arbitrary position on a step forming a gradation by just a prescribed thickness when flattening a layer with a gradation formed of a high position part and a low position part. Then the projecting part created after the etching existing more on the low position side than at the arbitrary position of the gradation is eliminated by heat treatment.
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Motorola Technical Developments, vol. 12, Apr. 1, 1991, pp. 59-64, XP000229266, Robinson F J: "Borophosphosilicte Glass Interlevel Dielectric Planarizatio n" *p. 59, col. 1, paragraph 4--p. 60, column 2, paragraph 2** figure 3*.
Ashigaki Shigeo
Hamamoto Kazuhiro
Donaldson Richard L.
Kempler William B.
Petersen Bret J.
Texas Instruments Incorporated
Tsai Jey
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