Method of making a self-aligned dopant enhanced RTA MOSFET

Details Method of making a self-aligned dopant enhanced RTA MOSFET Method of making a self-aligned dopant enhanced RTA MOSFET

1998-03-30

2000-07-18

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257330, H01L 2972

Patent

active

060911050

ABSTRACT:
An integrated circuit and a method of fabricating the same in a substrate are provided. A trench is formed in the substrate. The trench has a sidewall. A first insulating layer is formed on the sidewall. A gate electrode is formed on the first insulating layer. A first source/drain region is formed in the substrate and a second source/drain region is formed in the substrate. A first portion of the first source/drain region and a second portion of the second source/drain region are vertically spaced apart to define a channel region in the substrate. The process enables channel lengths to be set independent of the maximum resolution of the photolithographic system used to pattern the wafer. Very short channel lengths may be implemented.

REFERENCES:
patent: 5721442 (1998-02-01), Hong
Stanley Wolf and Richard N. Tauber Silicon Processing for the VLSI Era, Vol. 1: Process Technology, pp. 555-579, 1986.
Stanley Wolf and Richard N. Tauber, Silicon Processing for the VLSI Era, vol. 2: Process Integration, pp. 327-335, 493-496, 1990.

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