Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-12-18
2002-06-18
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
Reexamination Certificate
active
06406947
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to MOS Transistor and IC fabrication methods, and specifically to the fabrication of a low leakage dynamic threshold voltage metal oxide semiconductor (DTMOS) transistor on separation-by-implantation-of-oxygen (SIMOX) silicon or bulk silicon.
BACKGROUND OF THE INVENTION
A dynamic threshold voltage MOS (DTMOS) has been proposed in A dynamic threshold voltage MOSFET (DEMOS) for ultra-low voltage operation, by F. Assaderaghi et al., IEDM 94, 809 (1994), as providing a structure which will reduce the subthreshold swing in MOS devices. However, in most instances, the leakage current from the back bias to the source and to the drain will be high, and it is not possible to limit the operational voltage of such device to below 0.6 V. Operation at a voltage below 0.6V is desirable because such operation requires less power supply voltage.
SUMMARY OF THE INVENTION
A method of fabricating a dynamic threshold voltage metal oxide semiconductor (DTMOS) for operation at threshold voltages less than 0.6 volts includes preparing a silicon substrate to form a trench in an active area; forming a silicon layer in the trench, doping the silicon layer in the trench to form a highly doped layer, having a doping ion concentration in a range of between about 5.0·10
17
cm
−3
and 5.0·10
18
cm
−3
, depositing a silicon layer over the high doped silicon layer; and completing the structure to form a DTMOS transistor.
An object of the invention is to reduce the leakage currents of the DTMOS so that operational voltages lower than 0.6 are possible.
Another object of the invention is to construct a device according to the method of the invention which will reduce the junction capacitance thereof.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.
REFERENCES:
patent: 6255704 (2001-07-01), Iwata et al.
Kotaki, H. et al. “Novel bulk dynamic threshold voltage MOSFET (B-DTMOSO with advanced isolation (SITOS) and gate to shallow well contact (SSS-C) processes for ultra low power CMOS”, IEDM Technical Digest, IEEE, 1996, pp. 459-462.*
Article entitled, “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation”, by F. Assaderaghi, D. Sinitsky, S. Parke, J. Boker, P. K. Ko and C. Hu, published in 1994 IEEE, pp. 33.1.1 to 33.1.4.
LandOfFree
Method of making a low leakage dynamic threshold voltage MOS... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making a low leakage dynamic threshold voltage MOS..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a low leakage dynamic threshold voltage MOS... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2910724