Method of making a high performance, small area thin film transi

Details Method of making a high performance, small area thin film transi Method of making a high performance, small area thin film transi

1983-11-08

1985-09-24

Downey, Mary F.

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

430316, 430317, 430318, 430319, 430325, 430326, 357 237, 357 234, 252 794, 156643, G03C 500, H01L 2978

Patent

active

045433208

ABSTRACT:
A method of making a high performance, small area thin film transistor having a drain region, an insulating layer, and a source region forming a non-coplanar surface with respect to a substrate is disclosed. The insulative layer is formed in between the source and drain regions. A deposited semiconductor overlies the non-coplanar surface to form a current conduction channel between the drain and source. A gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent thereto. The non-coplanar surface can be formed by utilizing a dry process to simultaneously etch through several layers in a continuous one-step process. A second dielectric layer may be formed above the three previous layers. This decouples the gate electrode from the source region by creating two capacitances in series, thereby limiting the capacitance between the gate electrode and the source region.

REFERENCES:
patent: 3669661 (1972-06-01), Page et al.
patent: 3839177 (1974-10-01), Dimigen
Bondur et al., IBM Technical Disclosure Bulletin, vol. 19, No. 9, Feb. 1977.

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