Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2006-03-28
2006-03-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S311000
Reexamination Certificate
active
07018873
ABSTRACT:
provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.
REFERENCES:
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 5346839 (1994-09-01), Sundaresan
patent: 5773331 (1998-06-01), Solomon et al.
patent: 5929479 (1999-07-01), Oyama
patent: 6339002 (2002-01-01), Chan et al.
patent: 6342717 (2002-01-01), Komatsu
patent: 6496034 (2002-12-01), Forbes et al.
patent: 6528376 (2003-03-01), Guo
patent: 6541345 (2003-04-01), Komatsu
patent: 6580132 (2003-06-01), Chan et al.
patent: 6762101 (2004-07-01), Chan et al.
patent: 6946696 (2005-09-01), Chan et al.
patent: 2004/0119102 (2004-06-01), Chan et al.
patent: WO 02/101811 (2002-12-01), None
Stanley Wolf and Richard N. Tauber, Silicon Processing For The VLSI Era, 1986 Lattice Press, vol. 1, pp. 303-308.
Stanley Wolf, Silicon Processing For The VLSI Era, 1990, Lattice Press, vol. II, pp. 45-47 and 144-146.
Guarini K W, et al., “Triple-self aligned, planar double-gate MOSFETs: devices and circuits” International Electron Devices Meeting 2001. IEDM. Technical Digest. Washington, DC, Dec. 2-5, 2001, New York, NY: IEEE, US, Dec. 2, 2001, pp. 1921-1924.
Dennard Robert H.
Haensch Wilfried E.
Hanafi Hussein I.
Cheung, Esq. Wan Yee
Isaac Stanetta
Niebling John F.
Scully , Scott, Murphy & Presser, P.C.
LandOfFree
Method of making a device threshold control of front-gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making a device threshold control of front-gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a device threshold control of front-gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3612161