Method of making a damascene metallization

Details Method of making a damascene metallization Method of making a damascene metallization

1997-03-05

1998-04-07

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438625, 438626, 438634, 438638, 156DIG652.1, 156DIG653.1, H01L 214763

Patent

active

057364575

ABSTRACT:
A semiconductor process and structure is provided for use in single or dual damascene metallization processes. A thin metal layer which serves as an etch stop and masking layer is deposited upon a first dielectric layer. Then, a second dielectric layer is deposited upon the thin metallization masking layer. The thin metallization masking layer provides an etch stop to form the bottom of the in-laid conductor grooves. In a dual damascene process, the thin metallization masking layer leaves open the via regions. Thus, the conductor grooves above the metallization masking layer and the via regions may be etched in the first and second dielectrics in one step. In a single damascene process, the thin metallization etch masking layer may cover the via regions. The etch stop and masking layer can be formed from any conductive or non-conductive materials whose chemical, mechanical, thermal and electrical properties are compatible with the process and circuit performance.

REFERENCES:
patent: 3844831 (1974-10-01), Cass et al.
patent: 3865624 (1975-02-01), Wilde
patent: 3961414 (1976-06-01), Humphreys
patent: 4184909 (1980-01-01), Chang et al.
patent: 4536951 (1985-08-01), Rhodes et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4832789 (1989-05-01), Cochran et al.
patent: 5100816 (1992-03-01), Rodder
patent: 5141897 (1992-08-01), Manocha et al.
patent: 5284801 (1994-02-01), Page et al.
patent: 5286674 (1994-02-01), Roth et al.
patent: 5354711 (1994-10-01), Heitzmann et al.
patent: 5380680 (1995-01-01), Choi
patent: 5399527 (1995-03-01), Tabara
patent: 5451543 (1995-09-01), Woo et al.
patent: 5462893 (1995-10-01), Matsuoka et al.
patent: 5466639 (1995-11-01), Ireland
patent: 5470788 (1995-11-01), Biery et al.
patent: 5518963 (1996-05-01), Park
patent: 5534462 (1996-07-01), Fiordalice et al.
patent: 5543360 (1996-08-01), Matsuoka et al.
Dalal et al., "A Dual Damascene Hard Metal Capped CU and Al-Alloy for Interconnect Wiring of Ulsi Circuits," IEEE, IEDM 93 273-276 (1993).
Givens et al., "A Low-Temperature Local Interconnect Process in a 0.25.mu.m-Chanel CMOS Logic Technology with Shallow Trench Isolation," VMIC Conference, pp. 43-48 (Jun. 7-8, 1994).
Kaanta et al., "Dual Damascene: A UlSI Wiring Technology," VMIC Conference, pp. 144-152 (Jun. 11-12, 1991).
Kikuta et al., "Multilevel Planarized-Trench-Aluminum (PTA) Interconnection Using Reflow Sputtering and Chemical Mechanical Polishing," IEEE, IEDM 93 285-288 (1993).
Lakshminarayanan et al., "Dual Damascene Copper Metallization Process Using Chemical-Mechanical Polishing," VMIC Conference, pp. 49-55 (Jun. 7-8, 1994).
Kikuta et al., Aluminum-Germanium-Copper Multilevel Damascene Process Using Low Temperature Reflow Sputtering and Chemical Mechanical Polishing, IEEE IEDM 94-101, pp. 5.2.1-5.2.4.

Affiliated with

Also associated with

Rating

Method of making a damascene metallization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making a damascene metallization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a damascene metallization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-12881