Method of maintaining data coherency in a computer system having

Details Method of maintaining data coherency in a computer system having Method of maintaining data coherency in a computer system having

1997-10-20

2000-07-04

Nguyen, Hiep T

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711121, 711143, 711144, 711153, 711156, 711173, 709214, 709215, 709218, 709219, 710129, 710131, G06F 1216

Patent

active

06085295&

ABSTRACT:
A method of providing coherent shared memory access among a plurality of shared memory multiprocessor nodes. For each line of data in each of the nodes, a list of those processors of the node that have copies of the line in their caches is maintained. If a memory command is issued from a processor of one node, and if the command is directed to a line of memory of another node, then the memory command is sent directly to an adapter of the one node. When the adapter receives the command, it forwards the command from the one adapter to another adapter of the other node. When the other adapter receives the command, the command is forwarded to the local memory of the other node. The list of processors is then updated in the local memory of the other node to include or exclude the other adapter depending on the command. If the memory command is issued from one of the processors of one of the nodes, and if the command is directed to a line of memory of the one node, then the command is sent directly to local memory. When the local memory receives the command and if the adapter of the node is in the list of processors for a line associated with the command and if the command is a write command, then the command is forwarded to the adapter of the one node. When the adapter receives the command, the command is forwarded to remote adapters in each of the remote nodes which have processors which have cache copies of the line. Finally, when the latter remote adapters receive the command, the command is forwarded to the processors having the cache copies of the line.

REFERENCES:
patent: 5535365 (1996-07-01), Barriuso et al.
patent: 5749095 (1998-05-01), Hagersten
patent: 5787476 (1998-07-01), Laudon et al.
patent: 5829035 (1998-10-01), James et al.

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