Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-02-03
2008-12-09
Sough, Hyung (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S140000, C711S156000, C712S023000, C712S216000, C712S217000, C712S218000, C712S219000
Reexamination Certificate
active
07464242
ABSTRACT:
A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present invention introduces a cache hit or cache miss input into the load/store dependency logic. If the incoming load operation is a cache hit, then the quadword boundary address value is used for detection. If the incoming load operation is a cache miss, then the cacheline boundary address value is used for detection. This invention enhances the performance of LHS and LHR operations in a memory system.
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Barrick Brian David
Hicks Dwain Alan
Osanai Takeki
Ray David Scott
Carr LLP
International Business Machines - Corporation
Patel Kaushikkumar
Sough Hyung
Talpis Matt
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