Method of isolating a SRAM cell

Details Method of isolating a SRAM cell Method of isolating a SRAM cell

2000-04-04

2001-10-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S149000, C365S154000, C365S190000, C257S369000, C257S372000

Reexamination Certificate

active

06301148

ABSTRACT:

TECHNICAL FIELD
The invention relates to non-volatile static memory devices. More particularly, the invention relates to methods of manufacturing static random access memory devices.
BACKGROUND OF THE INVENTION
One known type of static read/write memory cell is a high-density static random access memory (SRAM). A static memory cell is characterized by operation in one of two mutually-exclusive and self-maintaining operating states. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a “high” voltage to indicate a “set” operating state. The memory cell output produces a “low” voltage to indicate a “reset” operating state. A low or reset output voltage usually represents a binary value of zero, while a high or set output voltage represents a binary value of one.
A static memory cell is said to be bistable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The two possible output voltages produced by a static memory cell correspond generally to upper (V
cc
internal−V
T
) and lower (V
ss
) circuit supply voltages. Intermediate output voltages, between the upper (V
CC
−V
T
) and lower (V
SS
) circuit supply voltages, generally do not occur except for during brief periods of memory cell power-up and during transitions from one operating state to the other operating state.
The operation of a static memory cell is in contrast to other types of memory cells such as dynamic cells which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, blut requires periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods.
A dynamic memory cell has no internal feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, resulting in loss of data. Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the six transistors typically required in a static memory cell. Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along generally different paths than has the design of dynamic memories.
A static memory cell
10
is illustrated in FIG.
1
. Static memory cell
10
generally comprises first and second inverters
12
and
14
which are cross-coupled to form a bistable flip-flop. Inverters
12
and
14
are formed by first and second n-channel pulldown (driver) transistors Ni and N
2
, and first and second p-channel load (pullup) transistors P
1
and P
2
. Transistors N
1
and N
2
are typically metal oxide silicon field effect transistors (MOSFETs) formed in an underlying silicon semiconductor substrate. P-channel transistors P
1
and P
2
can be thin film transistors formed above the driver transistors or bull devices.
Driver transistors N
1
and N
2
have respective source: regions
66
and
68
tied to a low reference or circuit supply voltage, labelled V
ss
, and typically referred to as “ground.” Driver transistors N
1
and N
2
have respective drain regions
64
and
62
, and respective gates. Load transistors P
1
and P
2
have respective source regions
78
and
80
tied to a high reference or circuit supply voltage, labelled V
cc
, and have respective drain regions
70
and
72
tied to the drains
64
and
62
, respectively, of the corresponding driver transistors N
1
and N
2
. The gate of load transistor P
1
is connected to the gate of driver transistor N
1
. The gate to load transistor P
2
is connected to the gate of the driver transistor N
2
.
Inverter
12
has an inverter output
20
formed by the drain of driver transistor N
1
. Similarly, inverter
14
has an inverter output
22
formed by the drain of driver transistor N
2
. Inverter
12
has an inverter input
76
formed by the gate of driver transistor N
1
. Inverter
14
has an inverter input
74
formed by the gate of driver transistor N
2
.
The inputs and outputs of inverters
12
and
14
are cross-coupled to form a flip-flop having a pair of complementary two-state outputs. Specifically, inverter output
20
is coupled to inverter input
74
via line
26
, and inverter output
22
is coupled to inverter input
76
via line
24
. In this configuration, inverter outputs
20
and
22
form the complementary two-state outputs of the flip-flop.
A memory flip-flop such as that described typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors
30
and
32
, are used to selectively address and access individual memory elements within the array. Access transistor
30
has one active terminal
58
connected to cross-coupled inverter output
20
. Access transistor
32
has one active terminal
60
connected to cross-coupled inverter output
22
. A pair of complementary column or bit lines
34
and
36
are connected to the remaining active terminals
56
and
54
of access transistors
30
and
32
, respectively. A row or word line
38
is connected to the gates of access transistors
30
and
32
. In the illustrated embodiment, access transistors
30
and
32
are n-channel transistors.
Reading static memory cell
10
requires activating row line
38
to connect inverter outputs
20
and
22
to column lines
34
and
36
. Writing to static memory cell
10
requires complementary logic voltage on column lines
34
and
36
with row line
38
activated. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
In semiconductor processing, there is a continuing desire to make circuits denser, and to place components closer and closer together to reduce the size of circuits. However, certain processing steps employed in manufacturing static memory cells such as the static memory cell shown in
FIG. 1
result in some undesirable variations between desired results and actual results in the manufacturing process. For example, there are precision limits inherent in photolithography. Another process that results in some undesirable variations between desired results and actual results is called LOCOS isolation (for LOCal Oxidation of Silicon). LOCOS isolation is a common technique for isolating devices.
Implementing a static memory cell on an integrated circuit involves connecting isolated circuit components or devices, such as flverters and access transistors, through specific electrical paths. When fabricating integrated circuits into a semiconductor substrate, devices within the substrate must be electrically isolated from other device s within the substrate. The devices are subsequently interconnected to create specific desired circuit configurations.
LOCOS isolation involves the formation of a semi-recessed oxide in the non-active (or field) areas of the bulk substrate. Such oxide is typically thermally grown by means of wet oxidation of the: bulk silicon substrate at temperatures of around 1000° C. for two to six hours. The oxide grows where there is no masking material over other silicon areas on the substrate. A typical masking material used to cover areas where field oxide is not desired is nitride, such as Si
3
N
4
.
However, at the edges of a nitride mask, some of the oxidant also diffuses laterally immedi

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