Method of ion implantation for adjusting the threshold...

Details Method of ion implantation for adjusting the threshold... Method of ion implantation for adjusting the threshold...

1999-07-14

2001-04-24

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S302000, C257S372000

Reexamination Certificate

active

06221703

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an ion implantation method, and more particularly, to an ion implantation method for adjusting the threshold voltage of MOS transistors.
2. Description of the Prior Art
The metal-oxide semiconductor (MOS) transistor is an electric component commonly used in integrated circuits. MOS transistors are four-connecting-point components composed of a gate, a source and a drain.
Please refer to FIG.
1
.
FIG. 1
is a perspective diagram of a prior art MOS transistor
40
on a semiconductor wafer
10
. The MOS transistor
40
comprises a gate
22
, source
30
and drain
32
. Shallow trenches
14
or FOX (field oxide) positioned around the MOS transistor
40
isolate it from other components.
Please refer to
FIG. 2
to FIG.
4
.
FIG. 2
to
FIG. 4
are perspective diagrams of producing the MOS transistor
40
in FIG.
1
. First, shallow trenches
14
are formed on the P-type Si substrate
12
of the semiconductor wafer
10
. Dopants B
11
or BF
2
+
are implanted in areas surrounding the shallow trenches
14
to form an impurity region
16
. This is accomplished by ion implantation at a threshold voltage V
t
and dosage of 5×10
11
~5×10
12
atoms/cm
2
. Then, thermal oxidation is performed to form a 40~®Å silicon oxide layer on the surface of the Si substrate
12
followed by in-situ phosphorus doped LPCVD to form a 500~1000 Å poly-silicon layer on the surface of the silicon oxide layer. The silicon oxide layer and poly-silicon layer are etched by photolithography and etching to severally form a gate insulating layer
18
and gate conducting layer
20
with rectangular-shaped cross sections. This completes formation of the gate
22
.
Then, an ion implantation process is performed to implant dopants P
31
or As
75
to form an N
−
lightly doped source
24
and drain
26
between the gate
22
and shallow trenches
14
. A spacer
28
is then formed at two sides of the gate
22
. Then, another ion implantation process is performed to implant dopants As
75
to form an N
+
heavily doped source
30
and drain
32
between the spacer
28
and shallow trenches
14
. This completes the formation of the MOS transistor
40
of N-channel shown in FIG.
1
.
As the size of the memory cell of the dynamic random access memory (DRAM) gets smaller, the width between the channel below the gate
22
of the MOS transistor
40
and the spacer
28
is smaller. Therefore, the impurity concentration of the impurity region
16
increases in proportion.
The impurity dosage required to form the source and drain is much greater than the dosage required to adjust the threshold voltage. When the dosage to adjust the threshold voltage is increased, the dosage of the source and drain is increased proportionately. However, as the dosage of the source and drain is increased, the junction leakage and junction capacitance of the MOS transistor
40
is greatly increased. But, when the dosage of the source
24
and drain
26
is decreased, the saturated drain current (I
dsant
) of the MOS transistor is reduced which makes it difficult for the capacitance of the memory cell of DRAM to read and write signals.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of ion implantation for adjusting the threshold voltage of MOS transistors. The junction leakage and junction capacitance of the MOS transistor thus formed are reduced.
Briefly, in a preferred embodiment, the present invention provides a method of ion implantation for adjusting the threshold voltage of a metal-oxide semiconductor (MOS) transistor. The MOS transistor is employed in a DRAM (dynamic random access memory) memory cell in a semiconductor wafer and comprises a substrate, a gate insulating layer positioned on the substrate, and a gate conducting layer with a rectangular-shaped cross section positioned on the gate insulating layer. The method comprises: performing an ion implantation process at a predetermined dosage and ion energy to implant dopants through the gate conducting layer and gate insulating layer and deposit the dopants into the surface portion of the substrate below the gate insulating layer.
It is an advantage of the present invention that the method according to the present invention can generate an MOS transistor with a smaller gate and a reduced impurity dosage of the source and drain of the MOS transistor. Thus, the MOS transistor has a lower junction leakage and junction capacitance while the saturated drain current (I
dsant
) of the MOS transistor is not reduced correspondingly. This prevents difficulties in reading and writing signals by the capacitance of the memory cell.
These and other objects and the advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 5399895 (1995-03-01), Koga
patent: 6020244 (2000-02-01), Thompson et al.
patent: 6034396 (2000-03-01), Wu

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