Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-02-08
2005-02-08
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S253000, C438S396000
Reexamination Certificate
active
06852628
ABSTRACT:
The process is used to electrically insulate adjacent metallic interconnects made from an aluminum-containing alloy, in particular for interconnects which are arranged on a DRAM cell array. A dielectric material is applied to the interconnects and the polymerizable material polymerizes under the action of heat. In a heat-treatment step the dielectric material is polymerized. A step of applying the dielectric material is carried out without a step of applying an interlayer between interconnects and dielectric material. On account of the self-passivation effect of aluminum, a thin Al2O3film, which protects the interconnect from corrosion, is formed on the interconnects.
REFERENCES:
patent: 5260600 (1993-11-01), Harada
patent: 5362686 (1994-11-01), Harada
patent: 5693566 (1997-12-01), Cheung
patent: 5858547 (1999-01-01), Drage
patent: 6015457 (2000-01-01), Leung et al.
patent: 6124165 (2000-09-01), Lien
patent: 6171945 (2001-01-01), Mandal et al.
patent: 6291628 (2001-09-01), Chen et al.
patent: 6300252 (2001-10-01), Ying et al.
patent: 6525398 (2003-02-01), Kim et al.
patent: 20010005609 (2001-06-01), Lee
patent: 0 680 085 (1995-11-01), None
patent: 0 551 306 (1995-12-01), None
patent: WO 0051174 (2000-08-01), None
A. Chin et al.: “Device and reliability of high-AI203 gate dielectric with good mobility and low D_it”,1999 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan, Jun. 14-16, 1999, Japan Soc Appl Phys 1999, pp. 135-136.
S. McClatchie et al.: “CVD low-k for gap fill & planarisation”,European Semiconductor, Aug. 1999, pp. 32-33.
V. Kottler et al.: An in situ X-ray photoelectron spectroscopy study of AIO/sub x/ spin tunnel barrier formation.Journal of Applied Physics. Mar. 15, 2001. vol. 89. No. 6, pp. 3301-3306.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nhu David
Stemer Werner H.
LandOfFree
Method of insulating interconnects, and memory cell array... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of insulating interconnects, and memory cell array..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of insulating interconnects, and memory cell array... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3461343