Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1997-07-18
2000-06-20
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
G06F 1210
Patent
active
060790040
DESCRIPTION:
BRIEF SUMMARY
This invention refers to a method for operating an address translation device for translating a virtual address into a physical address, the translation device being designed as a (direct-mapped or n-way set-associative) translation lookaside buffer (TLB), and the method allowing to avoid systematic clashing.
Modern processors use TLBs for a fast translation of virtual into physical addresses. Typically, the TLB and the cache are located on the processor chip.
A TLB is a special cache for address translation. While fully set-associative TLBs are also employed, TLBs are generally n-way set-associative. FIG. 4 illustrates a direct-mapped TLB, i.e. a 1-way set-associative TLB. The high-order portion v' (first address portion) of the virtual address v is used to address a line of the TLB. There, (in a tag field,) the virtual page address v'.sub.i associated with this entry, the physical page address r'.sub.i contained in a data field associated with the tag field, and status bits not shown in the Figure can be found, the status bits also indicating the validity of the entry. If it is valid, and v'.sub.i matches the present page address v', there is a TLB hit and the physical address is combined from the lower-order portion v" (second address portion) of the virtual address and the physical page address r'.sub.i provided by the TLB.
An n-way set-associative TLB differs from a direct-mapped TLB in that a plurality of marking and data fields are included in one entry, which are addressed simultaneously and are checked in parallel against v'. A hit is given when the contents of a tag field of the indexed TLB entry are correct; the, the r'.sub.i and the status bits thereof are used to form the physical address r and for access validation.
For large address spaces, a direct-mapped or n-way set-associative TLB is to be designed that allows to systematically minimize clashing for optional working sets of virtual pages. Here, the term working set means the number of all virtual pages presently in use, while "clashing" refers to a conflict between the virtual pages contained in the TLB.
To solve this object, an operating method for a TLB address translation device is provided, the method steps thereof being mentioned in claim 1. The method steps stated in the subclaims concern advantageous embodiments of the invention.
The present method serves to operate an address translation device for translating a virtual address of a virtual address space comprising a plurality of pages into a physical address of a physical address space comprising a plurality of pages with the use of a translation lookaside buffer and a page table. Here, the virtual address can be divided into a first address portion and a second address portion. According to the present invention, the virtual address is associated with a routing code. The physical address also has first and second address portions. The two address portions of the virtual address and the physical address can in particular be the page number address portion for addressing a page in the virtual or the physical address space, respectively, and the offset address portion for addressing within a physical or virtual page. The translation lookaside buffer contains a plurality of entries, each of which comprises at least one tag field and at least one data field associated to the tag field (additionally, further fields for control information or the like, especially a validity/invalidity field, may be provided).
According to the invention, the address translation is performed in the following manner: routing code associated with the virtual address or by a mapping of the routing code associated with the virtual address, or it is indexed to an index by a mapping of the routing code associated with the virtual address and the first address portion of the virtual address. In contrast to conventional TLBs using a portion of the virtual address for indexing, the invention provides for an indexing of the TLB by the routing code, i.e. information that does not form a part of the virtual address
REFERENCES:
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patent: 4376297 (1983-03-01), Anderson et al.
Proceedings of 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Oct. 2-4, 1989, Cambridge, Massachusetts, Ramachandran et al., "Design of a memory Management Unit for Object-Based System", pp. 512-517.
Chan Eddie P.
International Business Machines Corp.
Verbrugge Kevin
LandOfFree
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