Method of increasing erase speed in memory arrays

Details Method of increasing erase speed in memory arrays Method of increasing erase speed in memory arrays

2005-11-07

2008-12-09

Menz, Laura M (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S510000

Reexamination Certificate

active

07462907

ABSTRACT:
A memory array and a method of increasing erase speed therein are provided. The memory array includes a plurality of memory devices organized in rows and columns, where a plurality of bitlines are oriented substantially parallel to one another along a first direction and a plurality of wordlines are oriented substantially parallel to one another along a second direction perpendicular to the first direction. Each memory device includes a pair of energy barriers within the substrate on opposite sides of the channel width. The energy barriers prevent hot holes from diffusing out from under the gate, thereby increasing erase speed.

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