Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-11-19
2001-04-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Combined with the removal of material by nonchemical means
C438S626000
Reexamination Certificate
active
06214745
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a chemical-mechanical polishing (CMP) method, and more particularly, to a CMP method that is capable of forming a highly planar surface by forming a dummy pattern.
2. Description of Related Art
As the level of integration of semiconductor devices increases, not enough area can be found on the surface of a silicon chip for forming all the necessary interconnects. To accommodate all interconnects resulting from a miniaturization of metal-oxide semiconductor (MOS) transistors, designs having two or more metallic layers are frequently employed. An inter-metal dielectric (IMD) layer is normally used as an isolating layer separating an upper and a lower metallic layer. The conductive line patterns of a metallic layer are normally buried within trenches, and connection between an upper and a lower conductive line pattern is achieved through a plug formed inside a via opening.
A conventional method of manufacturing interconnects includes the steps of forming a via opening in an inter-metal dielectric (IMD) layer, and then completely filling the via opening with a conductive material to form a plug. Thereafter, metallic lines are formed above the IMD layer. The metallic lines are formed by depositing a layer of metal over the IMD layer, and then performing conventional photolithographic and etching operations. However, when the metallic layer is etched, micro-bridges are frequently formed between neighboring metallic lines so that two metallic lines are linked, which leads to a short-circuiting condition.
To improve the situation of the micro-bridging effect, the metallic lines are formed by a damascene process. The method is to deposit a dielectric layer over the IMD layer after the plug is formed. The dielectric layer has a thickness roughly equal to the thickness of the subsequently formed metallic lines. Next, the dielectric layer is etched to form a trench pattern, and then metallic material is deposited into the trenches to form the metallic lines. Since there is no direct etching of the metallic layer, there is no micro-bridging effect.
Another method for eliminating the micro-bridging effect is known as a dual damascene process. Dual damascene process is very similar to a damascene process. The main difference is that a damascene process is carried out after the plug is formed. On the other hand, the via opening and the trench pattern in a dual damascene process are formed at the same time so that conductive material can be deposited in a single operation to form the interconnects.
For clarity of explanation, the trench pattern in a damascene process and the via opening plus the trench pattern in a dual damascene process will be referred to as “damascene pattern” from now on.
In both damascene and dual damascene process, the conductive material above the dielectric layer needs to be removed after the damascene pattern is completely filled. A chemical-mechanical polishing method can be used to remove the excess conductive material above the dielectric layer while obtaining a planar surface at the same time.
FIGS. 1A through 1E
are cross-sectional views showing the progression of manufacturing steps in producing an interconnect that uses a chemical-mechanical polishing method to remove excess metal according to a conventional dual damascene process.
First, as shown in
FIG. 1A
, a conductive layer
12
is formed over a substrate
10
. Thereafter, a dielectric layer
14
and an etching stop layer
16
are sequentially formed over the conductive layer
12
. The dielectric layer
14
can be a silicon oxide (SiO
x
) layer, and the etching stop layer
16
can be a silicon nitride (SiN
x
) layer, for example. Then, a patterned photoresist layer
18
is formed over the etching stop layer
16
. The patterned photoresist layer
18
is used for marking out the area for forming a via opening. Subsequently, the etching stop layer
16
is etched to form an opening using the photoresist layer
18
as a mask. The etching stop layer
16
is later used as a mask for patterning out the via opening.
Next, as shown in
FIG. 1B
, the photoresist layer
18
is removed, and then another dielectric layer
24
is formed over the etching stop layer
16
.
Next, as shown in
FIG. 1C
, another patterned photoresist layer
28
is formed over the dielectric layer
24
. The photoresist layer
28
is used to pattern out the trench region in the dielectric layer
24
. In the subsequent step, a dry etching method, for example, is used to pattern the dielectric layer
24
, thereby exposing the etching stop layer
16
. Consequently, the dielectric layer
24
becomes a dielectric layer
24
a
having an opening pattern or trench
25
within. Thereafter, using the etching stop layer
16
as a mask, the dry etching operation is continued until a portion of the conductive layer
12
is exposed. Hence, the dielectric layer
14
becomes a dielectric layer
14
a having a via opening
23
within.
Next, as shown in
FIG. 1D
, the photoresist layer
28
is removed, and then a glue/barrier layer
21
conformal to the surface profile of the substrate
10
is formed over the substrate
10
. The glue/barrier layer
21
can be a tantalum nitride layer (TaN
x
) for example. Subsequently, a metallic layer
22
is formed over the glue/barrier layer
21
completely filling the via opening
23
and the trench
25
.
Next, as shown in
FIG. 1E
, a chemical-mechanical polishing operation is carried out to remove excess metallic material and glue/barrier layer
21
above the dielectric layer
24
a
Hence, the metallic layer
22
becomes a metallic layer
22
a
and the glue/barrier layer
21
becomes a glue/barrier layer
21
a.
However, there is a direct relationship between over-polishing time and polishing selectivity between the metallic layer
22
and the glue/barrier layer
21
. When the polishing selectivity between the two layers is large, polishing time needs to be extended. In general, the metallic layer
22
has a higher polishing rate than the glue/barrier layer
21
. Hence, when the glue/barrier layer
21
is exposed, the higher metallic content
22
a
of damascene pattern in the dense area
27
makes it easier to remove. Consequently, its neighboring glue/barrier layer
21
is also easier to remove. On the other hand, the damascene pattern in the open area
29
has a lower metallic content
22
a
, thereby making it difficult to remove.
In other words, the damascene pattern in the dense area
27
has a higher rate of removal than the damascene pattern in the open area
29
. Consequently, time necessary for completely removing the glue/barrier layer
21
in the open area
29
will be greater than the time for removing the same glue/barrier layer
21
in the dense area
27
. In order to remove completely the glue/barrier layer in the open area
29
, areas such as the dense area
27
need to be over-polished. Therefore, an extra portion of the dielectric layer
24
a
in the dense area
27
will be polished away resulting in an eroded profile as shown in FIG.
1
E.
One method of avoiding the erosion of dielectric layer
24
a
in the dense area
27
of a damascene pattern is to form a plurality of dummy patterns in the open area
29
of the damascene pattern. Consequently, the combined dummy pattern and open area
29
density is roughly equivalent to the density in the dense area
27
. Hence, the rate of removal of glue/barrier layer is roughly the same in both the dense area
27
and the open area
29
.
FIGS. 2A through 2C
are cross-sectional views showing the steps in producing an interconnect using a chemical-mechanical polishing operation that has a higher polishing removal rate for a glue/barrier layer in the open area of a damascene pattern.
Since the steps leading to the structure as shown in
FIG. 2A
has already been described in
FIGS. 1A and 1B
, detailed description of previous manufacturing steps are omitted. First, as shown in
FIG. 2A
, a patterned photoresist layer
38
is formed over the dielectric layer
24
. The patterned photoresi
Huang Yimin
Lur Water
Wu Juan-Yuan
Yang Ming-Sheng
Hoang Quoc
Nelms David
United Microelectronics Corp.
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