Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-08-12
1999-11-30
Booth, Richard
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438682, H01L 213205, H01L 214763
Patent
active
059942100
ABSTRACT:
Sheet resistance of titanium silicide formed on silicon is diminished by enhancing formation of nucleation sites for the C-54 phase. Fluorine is introduced into silicon by either the implantation of BF.sub.2 or F, followed by creation of a cap oxide over the silicon surface. During subsequent annealing, fluorine outgasses, forming bubbles in the silicon. Upon removal of the cap oxide, the gas escapes and the silicon surface is pitted and uneven, enhancing subsequent formation of C-54 nucleation sites.
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Booth Richard
Lindsay Jr. Walter L.
National Semiconductor Corporation
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