Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Fluid growth step with preceding and subsequent diverse...
Reexamination Certificate
2001-06-01
2002-06-18
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Fluid growth step with preceding and subsequent diverse...
C438S497000, C438S500000, C438S503000, C438S507000, C438S700000, C438S703000
Reexamination Certificate
active
06406982
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon Japanese Patent Application Nos. 2000-167822 filed on Jun. 5, 2000, and 2000-313918 filed on Oct. 13, 2000, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of semiconductor device having a trench, especially, which is filled with a diffusion layer.
2. Related Arts
With regard to a semiconductor device having a trench filled with a diffusion layer, a manufacturing method for making a prototype of the device is shown in
FIGS. 8A
to
8
D.
As shown in
FIG. 21A
, a silicon substrate
201
having a silicon oxide film
202
formed on a surface thereof is prepared. Subsequently, after an opening portion is formed in the silicon oxide film
202
at a predetermined region by photo-etching, dry etching or wet etching is performed to form a trench
203
in the silicon substrate
201
by applying the silicon oxide film having the opening portion as a mask as shown in FIG.
21
B. After that, the trench
203
is filled with an epitaxial film
204
in which impurities are doped as shown in FIG.
21
C. Then, the epitaxial film
204
is polished by applying the silicon oxide film
202
as a stopper, so that a polycrystalline silicon layer
205
is flattened as shown in FIG.
21
D. Through the steps described above, the semiconductor device having the trench
203
filled with the diffusion layer is completed.
FIG. 22A
shows an enlarged cross sectional view of the semiconductor device shown in
FIG. 21B
after the trench
203
is formed.
FIG. 22B
shows an enlarged cross sectional view of the semiconductor device shown in
FIG. 21C
when the epitaxial film is formed. In the method described above, the silicon oxide film
202
is used both as the mask for forming the trench and as the stopper for flattening the epitaxial film. Therefore, the epitaxial film is formed on the silicon oxide film
202
which is left as it is after the trench is formed.
However, during the step shown in
FIG. 22B
, an opening width of the trench
203
becomes wider than that of the opening portion of the silicon oxide film
202
, so that an edge of the silicon oxide film
202
protrudes from an inner surface of the trench
203
in parallel to a surface of the silicon substrate so as to form a protrusion.
202
a
as shown in FIG.
22
A. Therefore, when the epitaxial film is grown in the step shown in
FIG. 21C
, polycrystalline silicon grows on the protrusion
202
a
, which causes increase of crystal defects in the epitaxial film
204
. Since a growth rate of polycrystalline silicon is larger than that of single crystal silicon, an opening portion of the trench
203
is shut up by polycrystalline silicon portion
205
. As a result, a void in filling the trench is generated in the trench
203
.
Other problem in the present invention is explained with reference to
FIGS. 26A and 26B
. These figures show schematic cross sectional views of a prototype device based on a cross sectional SEM image.
FIG. 26A
shows a schematic cross sectional view after a trench etching is performed.
FIG. 26B
shows a schematic cross sectional view after an epitaxial growth for filling the trench is performed.
In a condition that a silicon substrate having a (1 1 0) face orientation is used as a substrate, and that a trench is formed in this substrate at a width of 18 &mgr;m and a depth of 13.5 &mgr;m, increase of the crystal defects occurs in a part of epitaxial film formed on a bottom surface of the trench. This may be caused by a roughness of Si (1 1 0) face disposed on the bottom surface of the trench larger than that of Si (1 1 1) face disposed on side face of the trench.
SUMMARY OF THE INVENTION
The present invention is devised to solve the above problems, and has an object to provide a manufacturing method of a semiconductor device having a trench filled with diffusion layer. The other object of the present invention is to improve to fill a trench with an epitaxial film having high quality.
According to first aspect of the invention, after trench is formed by using a mask, at least an edge portion of the mask, which is disposed at an opening portion of the trench so as to protrude from an edge of the opening portion of the trench, is removed. After that, the trench is filled with an epitaxial film. In other words, when the trench is filled with an epitaxial film, an opening width of the mask is larger than that of the trench.
It is preferable that a protecting layer is formed on the mask, which is used for widen the opening width of the mask. The protecting layer may be constituted by multiple layers.
It is preferable that an inner wall of the trench is flattened before the trench is filled with the epitaxial film. This flattening treatment improves crystallinity of the inner wall of the trench. In other words, roughness and crystal defects are reduced by the flattening treatment.
A heat treatment in low pressure atmosphere including non-oxidizing gas or non-nitriding gas is applied as the flattening treatment.
Other objects and features of the present invention will become more readily apparent from a better understanding of the preferred embodiment described below with reference to the following drawings.
REFERENCES:
patent: 4466173 (1984-08-01), Baliga
patent: 4528745 (1985-07-01), Muraoka
patent: 5216275 (1993-06-01), Chen
patent: 5438215 (1995-08-01), Tihanyi
patent: 6040211 (2000-03-01), Schrems
patent: 6291310 (2001-09-01), Madson et al.
patent: 2001/0034109 (2001-10-01), Madson et al.
patent: 0053854 (1982-06-01), None
patent: 0975024 (2000-01-01), None
patent: 53-94775 (1978-08-01), None
patent: 59-232 439 (1984-12-01), None
Sato, T. et al. “A New Substrate Engineering for the Formation of Empty Space In Silicon (ESS) Induced by Silicon Surface Migration” (Apr. 2000),pp. 1-5. Abstract only.
Sakakibara Toshio
Tsuji Nobuhiro
Urakami Yasushi
Yamaguchi Hitoshi
Yamauchi Shoichi
Kielin Erik
Law Offices of David G. Posz
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