Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-14
2002-04-02
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S745000
Reexamination Certificate
active
06365503
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a method of manufacturing a semiconductor device and, more specifically, to a method of reducing electromigration in a semiconductor device during the manufacturing of the device.
BACKGROUND OF THE INVENTION
The ever increasing use of integrated circuits (ICs) within computer and telecommunications technologies and the desire to continually increase the speed and the packing densities of such ICs has prompted the semiconductor manufacturing industry to decrease the size of many of the components that comprise the conventional IC. Along with other components of the IC, the interconnect has continually decreased in size. Specifically, the width of the interconnects have substantially decreased, while the interconnect's length has only reduced slightly. What has resulted is a relatively long but narrow interconnect trace.
Unfortunately, however, a problem exists with respect to these narrow interconnects. The problem results from higher amounts of electromigration (EM) which becomes pronounced at high electrical current densities. Electrons having a presumably large amount of momentum, carry the atoms of the interconnect material from the negative end of the interconnect to the positive end, and as a result compressive stresses build up at the positive end and tensile stresses build up at the negative end, creating what is collectively called backstress. When the backstress is equal to the EM, no plastic deformation occurs. However, plastic deformation arises when the EM is greater than the backstress, which in turn may create voids in the metal. These voids increase the resistance of the device and may also cause IC failure. Thus, it is highly desirable to decrease the amount of electromigration that occurs in ICs.
The semiconductor manufacturing industry has attempted to address this EM problem in various ways. For example, one solution is to place barrier layers on top of and below the interconnect. With the use of the barrier layers, the IC manufacturing industry is able to provide an interconnect that is less prone to EM open failure as well as an interconnect capable of surviving higher current densities. Unfortunately, however, the barrier layers are not without problems. It has been found that these barrier layers will shunt a significant amount of current after the aluminum is removed. High Joule heating, caused by the current, can cause the layers to heat up and crack, thus causing the interconnect structure, and ultimately the semiconductor device, to fail.
Integrated circuits contain millions of tungsten plug vias to connect interlevel metal runners. The vias however are potential failure sites because the vias are favorable sites for electromigration failure due to atomic flux divergences. Unlike metal runners terminated by pads, the runners ended by tungsten vias have no reservoir to replenish during electromigration depletion. Additionally, via processes may affect the underlying metal integrity. For instance, non-conformal via barriers may expose aluminum to the tungsten fluoride (WF
6
) gas during chemical vapor deposition. Tungsten fluoride will react with aluminum to form high resistive compounds and cause IC open failure. Moreover, inappropriate post window cleans may leave contaminants near the via bottom, leading to open or functional failure.
Since the problem of electromigration is not completely addressed by present day processes, it is highly desirable to reduce electromigration wherever possible and as much as possible within the semiconductor structures that form the IC.
Accordingly, what is needed in the art is method of further reducing the amount of electromigration that occurs in a semiconductor device.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method of forming an electromigration resisting layer in a semiconductor device. In an exemplary embodiment, the method comprises depositing a corrosion inhibitor comprising an organic ligand containing oxygen, on a conductive layer of a semiconductor device wherein the conductive layer is susceptible to electromigration. The method further includes subjecting the corrosion inhibitor and the semiconductor device to a high temperature anneal to form an electromigration resisting layer on the conductive layer that reduces electromigration of the conductive layer.
In another advantageous embodiment, the present invention provides a method of forming an integrated circuit. In this particular aspect, the method includes: (1) forming openings in a dielectric layer located over transistors and to conductive layers, (2) depositing a corrosion inhibitor comprising an organic ligand on the conductive layers and within the openings wherein the conductive layers is susceptible to electromigration, (3) subjecting the corrosion inhibitor and the semiconductor device to a high temperature anneal to form an electromigration resisting layer on the conductive layers that reduces electromigration of the conductive layers, (4) forming conductive material in the openings to form interconnects, and (5) connecting the interconnects with the transistors to form an operative integrated circuit.
An integrated circuit is also provided by the present invention. In an illustrative embodiment, the integrated circuit includes interconnects located in dielectric layers located over transistors. The interconnects contact conductive traces and interconnect the transistors to form an operative integrated circuit. The integrated circuit also includes an electromigration resisting film located on at least one of the conductive traces and where the interconnect contacts the conductive trace. The electromigration resisting film provides a conductive trace having an average electromigration lifetime ranging from about 100 hours to about 200 hours.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 6133158 (2000-10-01), Obeng et al.
Yaw S. Obeng, R.S. Raghavan; “‘Back End’ Chemical Cleaning in Integrated Circuit Fabrication: A Tutorial”; Material Research Society Symposium Proc., vol. 477, 1997; pp. 145-157.
Huang Jia Sheng
Kang Seung H.
Oates Anthony S.
Obeng Yaw S.
Agere Systems Guardian Corp.
Le Dung A.
Nelms David
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