Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2003-02-04
2004-05-11
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185120, C365S185200, C365S185290
Reexamination Certificate
active
06735114
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of non-volatile memory devices and, more particularly, to a method of improving dynamic reference tracking for a memory unit having, for example, a plurality of charge trapping dielectric flash memory devices.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, can store data in a “double-bit” arrangement. That is, one bit can be stored using a memory cell on a first “side” of the memory device and a second bit can be stored using a complimentary memory cell on a second “side” of the memory device.
The memory unit can also be provided with one or more dynamic reference memory devices having charge storing cells similar to the charge storing cells of the core memory devices. The dynamic reference devices assist in reading the core memory devices. More specifically, the dynamic references are used as indicators of the data level (e.g., charge storage) behavior of the core memory. The dynamic reference cells are programmed to store an amount of charge such that the dynamic reference has a certain threshold voltage. Over time, the charge amount stored by the dynamic reference cells and other factors contributing to the threshold voltage of the dynamic reference device may change. These factors cause a corresponding change in the threshold voltage of the dynamic reference device. The change in dynamic reference device threshold voltage can be used by a logic circuit associated with the memory unit to account for drift in threshold voltage of the core memory devices.
In the past, the dynamic reference devices have been programmed prior to programming of the core memory devices. More specifically, the dynamic references are initially programmed during an erase configuration operation. The erase configuration operation “sets up” the core memory cells (e.g., places all core cells in a blank or erased state) for subsequent programming by a customer of the memory unit. As a result, the dynamic reference cells tend to age differently than the core cells. Also, the current loading when programming the dynamic references may not be the same as the current loading when programming the core cells. Since the dynamic references are programmed at a different time and under different conditions than the core cells, read margins of the dynamic reference devices versus the core memory devices may differ and read operation accuracy can suffer as a consequence. This is especially problematic over repeating program/erase (P/E) cycling of the memory unit.
As indicated, dynamic reference cells have conventionally been programmed during a erase configuration operation. Such an operation includes pre-programming core memory cells and the dynamic reference cells. Pre-programming of the cells can involve injecting a charge into charge storing regions of the cells. Thereafter, all of the programmed cells are erased. If any of the cells were over-erased, those over-erased cells can be soft-programmed such that each cell has an amount of charge corresponding to a predetermined blank state threshold voltage distribution. The erase configuration operation can conclude by programming the dynamic reference cells to store an appropriate amount of charge. At this point the memory unit is ready for use. For example, the core cells can be programmed. Programming the core cells can be carried out by a page program technique where groups of core cells (e.g., a selected number of core cells, such as about eight core cells) are sequentially programmed until all core cells to be programmed have been programmed. Following programming (e.g., in preparation for a read operation), the threshold voltages of the dynamic reference cells can be verified. If the threshold voltages have fallen below a specified value, the dynamic references can be refreshed. Refreshing the dynamic references may increase the above-mentioned difference in read margins between the dynamic references and core memory devices, especially over P/E cycling and/or aging where charge loss may occur in the various memory devices.
In view of the foregoing, there is a need in the art for improved dynamic reference device tracking with associated core memory devices of a flash memory unit.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is directed to a method of programming a memory unit having a plurality of dual cell core memory devices and at least one dual cell dynamic reference device. The method can include providing the memory unit, wherein the memory unit has been subjected to an erase configuration operation such that each cell of the core memory devices is in a blank state and wherein a threshold voltage of the at least one dynamic reference device is less than a charged program level threshold voltage; and programming the at least one dynamic reference and the core memory devices using a page programming routine.
According to another aspect of the invention, the invention is directed to a method of programming a memory unit having a plurality of dual cell core memory devices and at least one dual cell dynamic reference device. The method can include providing the memory unit, wherein the memory unit has been subjected to an erase configuration operation such that each cell of the core memory devices and of the at least one dynamic reference is in a blank state; pre-reading the at least one dynamic reference; and programming at least one cell of the at least one dynamic reference device and at least one cell of at least one core memory device with a program pulse.
According to yet another aspect of the invention, the invention is directed to a method of programming a memory unit having a plurality of dual cell core memory devices and at least one dual cell dynamic reference device. The method can include providing the memory unit, wherein the memory unit has been subjected to an erase configuration operation such that each cell of the core memory devices is in a blank state and wherein an amount of charge has been injected into at least one cell of the at least one dynamic reference device, the amount of charge establishing a threshold voltage of the dynamic reference device that falls between a blank program state and a charged program state; programming the at least one cell of the at least one dynamic reference device to the charged program state; and programming at least one cell of at least one core memory device to the charged program state.
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Ajimine Eric M.
Cleveland Lee
Haddad Sameer S.
Hamilton Darlene G.
Randolph Mark W.
Advanced Micro Devices , Inc.
Phan Trong
Renner , Otto, Boisselle & Sklar, LLP
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