Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-04-12
2002-12-17
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S532000
Reexamination Certificate
active
06495432
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating integrated circuit devices, and more particularly, to a method of improving a dual gate of a CMOS transistor to resist the boron-penetrating effect.
2. Description of the Prior Art
In the early stages of MOS transistor development, the gate is mainly made of metal, such as aluminum. However, metal cannot withstand high-temperature tempering in subsequent processes. Therefore, polysilicon possessing good interface characteristics on an oxide layer and the ability to withstand high-temperature processes is popularly employed to fabricate the gate. For general complementary MOS (CMOS) transistors, an n
+
-type polysilicon is used as the gate of an n-type channel MOS transistor and the gate of an p-type channel MOS transistor at the same time, referred to as a single poly scheme. Despite the single poly scheme's simple processes, the absolute value of the threshold voltage of the p-type MOS transistor is very great (>1). The bottleneck occurs when processing line widths are smaller than 0.35 &mgr;m, and the main problem is the short channel effect in the p-type MOS transistor.
A dual poly scheme is an advanced technique in fabricating the gate, which employs p
+
-type polysilicon to form the gate of the p-type MOS transistor so as to manufacture surface channel devices, but has more complicated processes. Since the surface channel devices, such as the p-type MOS transistor and the n-type MOS transistor, have better control over the short channel effect, utilizing the dual scheme to manufacture the surface channel devices has become the main technique in 0.25~0.18 &mgr;m line-width processing. With dual polysilicon structure, serious consideration should be made of the boron ions' penetration of the gate oxide layer of the p-type MOS transistor, and the resulting damage. If the boron ions penetrate through the gate oxide layer to the substrate, they will diminish the absolute value of the threshold voltage of the p-type MOS transistor and even disable the device, causing shutdown so as to break down the circuitry. It will also decrease the property and reliability of the gate oxide layer.
The main reason for the boron-penetrating effect is that the boron ion in the oxide layer has a high diffusion coefficient, thus the boron-penetrating effect frequently occurs in high-temperature processes, especially in deep micrometer processing for manufacturing super-thin gate oxide layers. The existence of the fluoride ions will accelerate the boron-penetrating effect when the BF
2
+
implantation substitutes the boron implantation in order to effectively form a shallow junction. Methods of restraining the boron-penetrating effect follow.
1. Grow a stacked polysilicon gate. The grain boundaries of the polysilicon layers can be mutually staggered, therefore the average value of the boron-diffusion path can be lengthened to delay the boron-diffusion effect. Nonetheless, the increase in relative steps will raise production costs, and the parasitic resistance of the gate will be enlarged.
2. Grow an amorphous silicon (a-Si) gate. Because the crystallized a-Si whose grain size is larger, the crystallized a-Si can delay the boron-diffusion effect. Also, the grain boundary of the crystallized a-Si can surround the fluoride ions to ease the boron-diffusion effect. Unfortunately, growing a-Si consumes much time, which decreases the boron activation and enlarges the parasitic resistance of the gate.
3. Dope the nitride ions into the polysilicon layer. The resulting B-N bonding delays the boron-diffusion effect. Also, the nitride ions existing on the interface between the polysilicon layer and the oxide layer can delay the boron-diffusion effect. Yet, since the existence of the nitride ions may decrease boron activation, the parasitic resistance of the gate will be increased as the concentration of nitride ions is increased.
4. Grow a very thin nitride-containing polysilicon layer by chemical vapor deposition (CVD) on an interface between polysilicon and oxide. The interface between polysilicon and oxide is utilized to obstruct the boron-diffusion effect so as to slow down the boron penetration. However, the nitride ions still increase the parasitic resistance of the gate.
5. The boron ion implantation substitutes the BF
2
+
implantation to solve the problem caused by the fluoride ions. However, it is not easy to form a shallow junction at the source/drain region by the boron ion implantation.
6. An oxynitride layer substitutes the conventional oxide layer.
SUMMARY OF THE INVENTION
In consideration of the deterioration of the thinned gate oxide layer caused by the boron-penetrating effect, the object of the present invention is to provide a method of improving a dual gate of the CMOS transistor to resist the boron-penetrating effect.
There is provided, in the present invention, to dope the boron ions into a polysilicon gate in order to prevent the boron-penetrating effect being accelerated by the fluoride ions. The BF
2
+
ions are then doped into the polysilicon gate to form an extended source/drain region and complete a shallow junction. A gate photoresist layer that is utilized to define a predetermined gate pattern fully stops the BF
2
+
ions entering the polysilicon gate so as to achieve self-alignment.
It is an advantage of the present invention that the p-type device is improved to have a better ability to resist the boron-penetrating effect and the super shallow junction is completed by the BF
2
+
ions. Also, the method of the present invention achieves the self-alignment result and has no need for extra processes and masks. Furthermore, the method is simply and practically applicable to mass production and integrated circuit processing.
REFERENCES:
patent: 5629221 (1997-05-01), Chao et al.
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5851889 (1998-12-01), Michael et al.
patent: 6001677 (1999-12-01), Shimizu
patent: 6030874 (2000-02-01), Grider et al.
patent: 6323094 (2001-11-01), Wu
Chang Chun-Yen
Chen Chi-Chun
Huang Tiao-Yuan
Lin Horng-Chih
Elms Richard
Fish & Richardson P.C.
National Science Council
Owens Beth E.
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