Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-12-03
2002-08-13
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000, C438S653000, C438S783000, C438S763000
Reexamination Certificate
active
06432808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to bond pads, and in particular to improving the bondability of bond pads.
2. Discussion of the Related Art
After fabrication, an integrated circuit is typically assembled into a package. The packaged IC is then used on a printed circuit board for use in a system. To provide an electrical connection between the IC and the package, a thin metal wire is bonded to an IC bonding pad and then wired to the appropriate inner lead of the package. This process is repeated for each bonding pad/inner lead.
FIG. 1
shows a prior art bond pad including a substrate
10
, a dielectric layer
12
, a barrier metal layer
14
, and a metal bonding layer
16
. Substrate
10
generically represents a semiconductor wafer, devices formed within the wafer, and layers formed on the wafer surface. Dielectric layer
12
includes, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or silicon oxide. Barrier metal layer
14
is typically formed from titanium nitride, titanium tungsten (TiW), titanium, or tungsten. After a passivation layer
18
is formed, a window
20
is opened, thereby defining a bond pad area
22
.
However, barrier metal layer
14
may not have adequate adhesion to dielectric layer
12
. Thus, during bonding of the bond pad to the metal wire (not shown), barrier layer
14
may separate from dielectric layer
12
. This bond pad lift off reduces bonding yields and/or reliability.
U.S. Pat. No. 5,834,365 describes a method to minimize bond pad lift off by forming conformal layers underlying the metal bonding layer. For example, referring to
FIG. 2
, a dielectric layer formed on a substrate
20
is divided into two dielectric layers
22
A and
22
B. Stripes or other patterns
23
, typically comprising polycide, polysilicon, TiW, TiN, or other metals, are formed on first dielectric layer
22
A. In this manner, subsequent formed layers, i.e. second dielectric layer
22
B and barrier metal layer
24
, are conformal to stripes
23
. The non-smooth surface of each of these layers was believed to improve adhesion between barrier metal layer
24
and dielectric layers
22
A and
22
B, thereby preventing bond pad lift off. However, depending on the composition of dielectric layers
22
A and
22
B, even forming stripes
23
and the subsequent conformal layers cannot eliminate some bond pad lift off.
Specifically, to reduce the dielectric constant, the industry has recently moved from using standard silicon dioxide in the dielectric layer to fluorinated silicon glass (FSG)(silicon dioxide combined with fluorine). The use of FSG lowers the dielectric constant in relative proportion to the concentration of fluorine. For example, a concentration of 5 to 15% fluorine in the dielectric layer reduces the associated dielectric constant by 5-15%. In one case, the addition of fluorine in the dielectric layer lowered the dielectric constant from 4.2 to 3.5. Lowering the dielectric constant in the dielectric layer advantageously reduces the metal to metal capacitance, which in turn improves the speed of the chip. However, the advantage of having a lower dielectric constant has been offset with the disadvantage of more instances of bond pad lift off.
Therefore, a need arises for a method of retaining fluorine in the dielectric layer, while at the same time minimizing bond pad lift off.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method of forming a bond pad area for an integrated circuit retains fluorine in the dielectric layer while at the same time minimizes bond pad lift off. The method includes forming a first dielectric layer comprising fluorinated silicon glass (FSG) layer on a substrate, then forming an FSG barrier layer on the first dielectric layer. A second, non-FSG dielectric layer is formed on the FSG barrier layer. A barrier metal layer is formed on the second dielectric layer. Finally, a metal layer is formed on the barrier metal layer. This metal layer provides the surface for adhesion to the bonding wire.
The first dielectric layer comprising FSG and the FSG barrier layer chemically interact. Specifically, the FSG barrier layer has dangling bonds, which absorb the atoms of fluorine diffused from the FSG layer. Thus, the FSG barrier layer minimizes any outgassing of fluorine into the second dielectric layer adjacent the barrier metal layer. In one embodiment, the FSG barrier layer includes titanium or aluminum. In this manner, the present invention provides a bond pad with a low dielectric constant while at the same time reduces bond pad lift off.
REFERENCES:
patent: 5763010 (1998-06-01), Guo et al.
patent: 5834365 (1998-11-01), Min-Tsung et al.
patent: 6008120 (1999-12-01), Lee
patent: 6010962 (2000-01-01), Liu et al.
patent: 6174797 (2001-01-01), Bao et al.
patent: 6217658 (2001-04-01), Orczyk et al.
patent: 6261157 (2001-07-01), Bajaj et al.
patent: 6265779 (2001-07-01), Grill et al.
patent: 6287956 (2001-09-01), Yokoyama et al.
Hart Michael J.
Karp James
Fahmy Wael
Garcia Joannie Adele
Harms Jeanette S.
Xilinx , Inc.
Young Edel M.
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