Method of implementing digital phase-locked loops

Details Method of implementing digital phase-locked loops Method of implementing digital phase-locked loops

1993-10-13

1997-02-11

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327150, H03D 324

Patent

active

056028830

ABSTRACT:
In a new formulation for digital phase-locked loops, loop-filter constants are determined from loop roots that can each be selectively placed in the s-plane on the basis of a new set of parameters, each with simple and direct physical meaning in terms of loop noise bandwidth, root-specific decay rate, and root-specific damping. Loops of first to fourth order are treated in the continuous-update approximation (B.sub.L T .fwdarw.0) and in a discrete-update formulation with arbitrary B.sub.L T. Deficiencies of the continuous-update approximation in large-B.sub.L T applications are avoided in the new discrete-update formulation.

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