Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1998-06-12
2002-04-16
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S101000, C326S037000
Reexamination Certificate
active
06373288
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to digital electronics, and, more particularly, to a method of implementing clock trees in synchronous digital electronic circuits, and to a programmable delay buffer stage therefor.
BACKGROUND OF THE INVENTION
As will be readily appreciated by one skilled in the art, one of the most exacting problems associated with making synchronous digital electronic circuits is the making of the so-called clocking or clock trees therein. A clock tree is a circuit portion designed to provide full synchronization for the operations of different sub-circuits included in a complex circuit system, such as a semiconductor integrated circuit.
The problems connected with the implementation of clock trees are reviewed, for example, in an article “Post-processing of Clock Trees via Wiresizing and Buffering for Robust Design”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 15, No. 6, June 1996. One typical problem to be addressed in designing clock trees is the delay time that hampers the clock signal through the various interconnection nodes between circuit portions of the system. In fact, there is a demand for minimizing the relative delay or “skew” of a clock signal being propagated through the various interconnection nodes of an electronic circuit where the signal is utilized.
The delay in propagating the clock signal along the circuit is tied to the capacitive load present on the various circuit branches. This capacitive load is, in turn, dependent on the ultimate construction of the integrated electronic circuit. Since at the designing stage of the clock tree the ultimate construction of the integrated circuit may still be unresolved as to details, the clock tree is usually sized on the basis of assumptions about the complexity of the finished circuit. Later on, once the overall construction of the integrated circuit is more complete or settled, the clock tree will be altered to adapt it to that construction.
This clock tree designing procedure implies some clear drawbacks arising since the circuit structures appointed to propagate the clock signal cannot be defined at an early stage of the designing procedure, and that subsequent processing is expensive and time consuming. Another drawback is that it is not always possible to adopt a common approach to the design of either a standard type of circuit structure using a CAD design assisting apparatus (standard cell), or a substantially manually designed (full custom) circuit.
Some attempted approaches to the implementation of clock trees in synchronous digital electronic circuits have been proposed in the prior art. A first approach is described in a paper “Clock Tree Synthesis Methodology” presented at the International Cadence Users Group Conference held in Boston in October 1985. A second prior approach is described in an article “Design Methodology for Synthesizing Clock Distribution Networks Exploiting Nonzero Localized Clock Skew”, IEEE Transactions on “Very Large Scale Integration (VLSI) Systems”, Vol. 4, No. 2, June 1996.
SUMMARY OF THE INVENTION
The present invention is aimed at improving on the methodologies disclosed in the above references. In particular, the present invention provides a method for forming clock trees in synchronous digital electronic circuits, and a programmable delay buffer stage therefor, which have functional and structural features to ensure adequate attenuation of the propagation skew and lower processing costs for the clock tree.
One aspect of the present invention uses a programmable delay buffer stage to provide clock trees with a desired predetermined amount of skew. Based on this principle, the shortcomings of the prior art are overcome by a method as previously indicated being characterized in that it provides for the use of buffer stages having a programmable delay.
The present invention also preferably provides a programmable delay buffer stage comprising at least one input terminal and at least one output terminal, and a plurality of inverters connected in series and/or parallel with one another between the input terminal and the output terminal to produce a desired predetermined amount of skew.
REFERENCES:
patent: 5376842 (1994-12-01), Honoa et al.
patent: 5831459 (1998-11-01), McDonald
Battaia Alberto
Ganzelmi Roberto
Pozzi Cesare
Allen Dyer Dopplet Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
STMicroelectronics S.r.l.
Tokar Michael
Tran Anh Q.
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