Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-30
2001-04-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S421000, C438S422000, C438S622000, C438S623000, C438S624000
Reexamination Certificate
active
06214719
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention, in general, relates to a semiconductor process, and more specifically, to a method of implementing air-gap technology in a semiconductor device so as to reduce parasitic capacitance between metal lines, improve the integrated circuit chip speed, and reduce power consumption and cross-talk.
2. Description of Related Art
As device dimensions continue to shrink, the parasitic effects of line to line capacitance becomes a critical factor to performance and circuit integrity. The RC delays associated with the interconnect metal lines of a semiconductor device have become a limiting factor to the speed of the device. Intra-level line-to-line capacitance increasingly dominates over inter-level capacitance, adding significant delay to the rise and fall times of the propagating signals. Reducing the capacitance between the interconnect metal lines on an integrated circuit chip will enhance the speed of the device and reduce extraneous signal energy (cross-talk) from traversing from one metal line to another.
Prior art attempts to reduce the RC delays have focused on utilizing material with a low dielectric constant to fill the gaps between the interconnect metal lines. A low dielectric constant reduces the capacitance associated with a given material. Silicon oxide (SiO
2
), which is typically placed between the metal lines, has a dielectric constant (k) of about 4.0-4.1.
Electrical current through the metal lines charges the insulating dielectric material between the lines. The time to charge is proportional to the dielectric constant of the material. Greater capacitance of the interconnecting material, i.e., a greater dielectric constant, will delay the rise and fall times of signals in the metal lines, thereby adversely affecting the chip speed.
It has been estimated that the RC interconnection delay could be reduced if the silicon oxide films, with a dielectric constant of approximately 4.0, could be replaced by films having a lower dielectric constant. Current low k dielectrics under investigation include fluorinated SiO
2
, aerogels, and polymers.
Polymers with dielectric constants on the order of k=2.5 have been used as the interconnecting material, but these materials are unstable under thermal treatment and throughout the chip fabrication process.
Another approach, leading to a reduction of the dielectric constant to about 3.3-3.8, involves the incorporation of bounded fluorine in silicon oxide films deposited by plasma chemical vapor deposition (PCVD) to form a fluorinated oxide. However, fluorine is also not stable and will degrade the metal lines that are in contact with it.
Porous materials have also been used between the interconnect metal lines. These materials, commonly referred to as aerogels, will yield dielectric constants on the order of k=1.9 to 2.0. However, they are extremely unstable during the fabrication process and are susceptible to shrinkage. These materials are also known to cause deleterious effects during chemical-mechanical polishing, a necessary process step in chip fabrication.
Prior art techniques have also included the introduction of air-gaps to reduce the capacitance between adjacent materials in a semiconductor device. U.S. Pat. No. 5,891,783 issued to Lin, et al., on Apr. 6, 1999, entitled “METHOD OF REDUCING FRINGE CAPACITANCE”, teaches the introduction of an air-gap formed between a gate and a substrate on a semiconductor device. According to the Lin invention, with the formation of the air-gap, the fringe capacitance between the gate and the substrate is reduced to the lower dielectric constant of air (k=1.0). Thus, the signal delay time is effectively shortened. This air-gap is formed during the removal of a silicon nitride layer. The thickness of the air-gap being the thickness of the removed silicon nitride.
The dielectric constant of air is about 1.0. Compared to the material of a conventional spacer, that is, silicon oxide or silicon nitride, the dielectric constant of air is significantly smaller, so that the capacitance of material having an air-gap therein is significantly reduced. Thus, air bridges in the interconnect metal line gaps would effectively achieve the greatest reduction in dielectric constant. However, mechanical rigidity and device reliability are compromised with air bridges. Also, chip to chip variations in device speed and power consumption are prevalent when air bridge gaps are introduced.
Although B. Shieh, et al., “AIR-GAP FORMATION DURING IMD DEPOSITION TO LOWER INTERCONNECT CAPACITANCE”, IEEE Electron Device Letters, Vol. 19, No. 1, January, 1998, pp. 16-18, shows a composite of an air-gap within SiO
2
is beneficial in mitigating the adverse affects of a non-composite air-gap bridge and reducing the interconnect capacitance, there is no disclosure or suggestion that such a composite structure could be implemented in a damascene scheme.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for decreasing the dielectric constant of the material between interconnect metal lines of a semiconductor substrate in a damascene scheme.
It is another object of the present invention to provide a method of increasing the speed of an integrated circuit chip in a plasma chemical vapor deposition fabrication process.
A further object of the invention is to provide a method for introducing air-gap technology in an ILD damascene scheme.
Still other advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method for establishing a low dielectric material between metal lines in a damascene scheme, comprising the steps of: a) providing a polished substrate; b) depositing a first dielectric layer on the substrate at a predetermined height and having a top surface; c) patterning and etching the first dielectric layer to form lines; d) depositing a second dielectric layer between the first dielectric layer lines and forming air gaps in the second dielectric layer, the air gaps formed below the predetermined height; e) polishing the substrate until the top surface of the first dielectric layer lines are exposed, while leaving lines of the second dielectric layer therebetween; f) etching and removing the first dielectric layer; and, g) depositing metal at the predetermined height and between the second dielectric layer lines.
Additionally, step (a) may further comprise providing a polished substrate having a pre-metal dielectric layer with vias connected to individual transistor contacts, or a polished substrate with metal lines and vias therein.
Polishing the substrate further comprises applying a chemical-mechanical polishing process. Etching and removing the first dielectric layer may comprise wet etching with hot phosphoric acid. Additionally, depositing metal further comprises depositing a barrier liner and seed layer for metal deposition, and depositing copper metal.
In a second aspect, the present invention relates to a method for implementing low dielectric lines between metal lines in a damascene scheme, comprising the steps of: a) providing a substrate having a substrate top surface; b) polishing the substrate top surface; c) depositing a silicon nitride layer on the substrate top surface; d) forming silicon nitride lines, the nitride lines having exposed top surfaces; e) depositing an oxide layer having an upper surface and forming air gaps therein such that the air gaps are located in the spaces between the nitride lines and below the nitride lines top surfaces; f) polishing the oxide layer and exposing the top surface of the nitride lines; g) removing the nitride lines such that oxide lines having air gaps therein remain on the substrate; h) depositing a metal layer between the oxide lines; and, i) polishing the met
Curcio Robert
DeLio & Peterson LLC
Nguyen Ha Tran
Niebling John F.
Novellus Systems Inc.
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